DCSURF_FLIP_CONTROL 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, DCSURF_FLIP_CONTROL 353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); DCSURF_FLIP_CONTROL 354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); DCSURF_FLIP_CONTROL 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); DCSURF_FLIP_CONTROL 359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); DCSURF_FLIP_CONTROL 727 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_FLIP_CONTROL, DCSURF_FLIP_CONTROL 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\ DCSURF_FLIP_CONTROL 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCSURF_FLIP_CONTROL; \ DCSURF_FLIP_CONTROL 616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); DCSURF_FLIP_CONTROL 631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); DCSURF_FLIP_CONTROL 685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, DCSURF_FLIP_CONTROL 693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); DCSURF_FLIP_CONTROL 694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); DCSURF_FLIP_CONTROL 698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); DCSURF_FLIP_CONTROL 699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); DCSURF_FLIP_CONTROL 891 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_FLIP_CONTROL,