cr_lcd            251 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
cr_lcd            258 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	*cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
cr_lcd            262 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			*cr_lcd |= head ? 0x0 : 0x8;
cr_lcd            264 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			*cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
cr_lcd            266 drivers/gpu/drm/nouveau/dispnv04/dfp.c 				*cr_lcd |= 0x30;
cr_lcd            267 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
cr_lcd            403 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
cr_lcd            433 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 		*cr_lcd |= 0x1 | (head ? 0x0 : 0x8);