cr9                17 arch/arm/include/asm/vfp.h #define FPINST			cr9
cr9               119 arch/parisc/include/asm/asmregs.h pidr2:	.reg	%cr9
cr9               146 arch/parisc/include/asm/asmregs.h cr9:	.reg	%cr9
cr9                63 arch/parisc/include/uapi/asm/ptrace.h 	unsigned long cr8, cr9, cr12, cr13, cr10, cr15;
cr9               479 arch/parisc/kernel/ptrace.c 	case RI(cr9):			return mfctl(9);
cr9               524 arch/parisc/kernel/ptrace.c         case cr8, cr9, cr12, cr13, cr10, cr15;
cr9               632 arch/s390/include/asm/kvm_host.h 	unsigned long cr9;
cr9               114 arch/s390/include/asm/ptrace.h 	unsigned long cr9;		/* PER control bits */
cr9                 9 arch/s390/kernel/compat_ptrace.h 	__u32 cr9;		/* PER control bits */
cr9               156 arch/s390/kernel/ptrace.c 	if (addr == (addr_t) &dummy->cr9)
cr9               315 arch/s390/kernel/ptrace.c 	if (addr == (addr_t) &dummy->cr9)
cr9               541 arch/s390/kernel/ptrace.c 	if (addr == (addr_t) &dummy32->cr9)
cr9               674 arch/s390/kernel/ptrace.c 	if (addr == (addr_t) &dummy32->cr9)
cr9                62 arch/s390/kvm/guestdbg.c 	u64 *cr9 = &vcpu->arch.sie_block->gcr[9];
cr9                75 arch/s390/kvm/guestdbg.c 	if (!(*cr9 & PER_EVENT_BRANCH))
cr9                76 arch/s390/kvm/guestdbg.c 		*cr9 |= PER_CONTROL_BRANCH_ADDRESS;
cr9                77 arch/s390/kvm/guestdbg.c 	*cr9 |= PER_EVENT_IFETCH | PER_EVENT_BRANCH;
cr9               102 arch/s390/kvm/guestdbg.c 	u64 *cr9 = &vcpu->arch.sie_block->gcr[9];
cr9               113 arch/s390/kvm/guestdbg.c 	if (*cr9 & PER_EVENT_STORE && *cr9 & PER_CONTROL_ALTERATION) {
cr9               114 arch/s390/kvm/guestdbg.c 		*cr9 &= ~PER_CONTROL_ALTERATION;
cr9               118 arch/s390/kvm/guestdbg.c 		*cr9 &= ~PER_CONTROL_ALTERATION;
cr9               119 arch/s390/kvm/guestdbg.c 		*cr9 |= PER_EVENT_STORE;
cr9               133 arch/s390/kvm/guestdbg.c 	vcpu->arch.guestdbg.cr9 = vcpu->arch.sie_block->gcr[9];
cr9               141 arch/s390/kvm/guestdbg.c 	vcpu->arch.sie_block->gcr[9] = vcpu->arch.guestdbg.cr9;
cr9               541 arch/s390/kvm/guestdbg.c 	u64 cr9 = vcpu->arch.sie_block->gcr[9];
cr9               545 arch/s390/kvm/guestdbg.c 	u8 guest_perc = perc & (cr9 >> 24) & PER_CODE_MASK;
cr9               554 arch/s390/kvm/guestdbg.c 	    cr9 & PER_CONTROL_BRANCH_ADDRESS &&
cr9                31 arch/sh/include/cpu-sh5/cpu/registers.h #define PSPC	cr9