DCP 35 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_UPDATE, DCP, id), \ DCP 36 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_CONTROL, DCP, id), \ DCP 37 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_POSITION, DCP, id), \ DCP 38 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_HOT_SPOT, DCP, id), \ DCP 39 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_COLOR1, DCP, id), \ DCP 40 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_COLOR2, DCP, id), \ DCP 41 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_SIZE, DCP, id), \ DCP 42 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \ DCP 43 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(CUR_SURFACE_ADDRESS, DCP, id), \ DCP 44 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(PRESCALE_GRPH_CONTROL, DCP, id), \ DCP 45 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \ DCP 46 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \ DCP 47 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \ DCP 48 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(INPUT_GAMMA_CONTROL, DCP, id), \ DCP 49 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \ DCP 50 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(DC_LUT_RW_MODE, DCP, id), \ DCP 51 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(DC_LUT_CONTROL, DCP, id), \ DCP 52 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(DC_LUT_RW_INDEX, DCP, id), \ DCP 53 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(DC_LUT_SEQ_COLOR, DCP, id), \ DCP 54 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h SRI(DEGAMMA_CONTROL, DCP, id) DCP 35 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_ENABLE, DCP, id),\ DCP 36 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_CONTROL, DCP, id),\ DCP 37 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_X_START, DCP, id),\ DCP 38 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_Y_START, DCP, id),\ DCP 39 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_X_END, DCP, id),\ DCP 40 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_Y_END, DCP, id),\ DCP 41 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_PITCH, DCP, id),\ DCP 42 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(HW_ROTATION, DCP, id),\ DCP 43 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_SWAP_CNTL, DCP, id),\ DCP 44 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(PRESCALE_GRPH_CONTROL, DCP, id),\ DCP 45 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_UPDATE, DCP, id),\ DCP 46 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_FLIP_CONTROL, DCP, id),\ DCP 47 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\ DCP 48 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\ DCP 49 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\ DCP 50 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\ DCP 58 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(DVMM_PTE_CONTROL, DCP, id),\ DCP 59 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(DVMM_PTE_ARB_CONTROL, DCP, id) DCP 67 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id) DCP 76 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ DCP 40 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(GAMUT_REMAP_CONTROL, DCP, id), \ DCP 41 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(GAMUT_REMAP_C11_C12, DCP, id), \ DCP 42 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(GAMUT_REMAP_C13_C14, DCP, id), \ DCP 43 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(GAMUT_REMAP_C21_C22, DCP, id), \ DCP 44 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(GAMUT_REMAP_C23_C24, DCP, id), \ DCP 45 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(GAMUT_REMAP_C31_C32, DCP, id), \ DCP 46 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(GAMUT_REMAP_C33_C34, DCP, id), \ DCP 47 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUTPUT_CSC_C11_C12, DCP, id), \ DCP 48 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUTPUT_CSC_C13_C14, DCP, id), \ DCP 49 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUTPUT_CSC_C21_C22, DCP, id), \ DCP 50 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUTPUT_CSC_C23_C24, DCP, id), \ DCP 51 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUTPUT_CSC_C31_C32, DCP, id), \ DCP 52 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUTPUT_CSC_C33_C34, DCP, id), \ DCP 53 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUTPUT_CSC_CONTROL, DCP, id), \ DCP 54 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \ DCP 55 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \ DCP 56 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \ DCP 57 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \ DCP 58 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \ DCP 59 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \ DCP 60 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \ DCP 61 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \ DCP 62 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \ DCP 63 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \ DCP 64 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \ DCP 65 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \ DCP 66 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \ DCP 67 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_LUT_INDEX, DCP, id), \ DCP 68 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_LUT_DATA, DCP, id), \ DCP 69 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(REGAMMA_CONTROL, DCP, id), \ DCP 70 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(DENORM_CONTROL, DCP, id), \ DCP 71 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \ DCP 72 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUT_ROUND_CONTROL, DCP, id), \ DCP 73 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \ DCP 74 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \ DCP 75 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \ DCP 138 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c IRQ_REG_ENTRY(DCP, reg_num, \ DCP 141 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\