cqc 1202 drivers/crypto/hisilicon/qm.c struct qm_cqc *cqc; cqc 1236 drivers/crypto/hisilicon/qm.c cqc = kzalloc(sizeof(struct qm_cqc), GFP_KERNEL); cqc 1237 drivers/crypto/hisilicon/qm.c if (!cqc) cqc 1239 drivers/crypto/hisilicon/qm.c cqc_dma = dma_map_single(dev, cqc, sizeof(struct qm_cqc), cqc 1242 drivers/crypto/hisilicon/qm.c kfree(cqc); cqc 1246 drivers/crypto/hisilicon/qm.c INIT_QC_COMMON(cqc, qp->cqe_dma, pasid); cqc 1248 drivers/crypto/hisilicon/qm.c cqc->dw3 = QM_MK_CQC_DW3_V1(0, 0, 0, 4); cqc 1249 drivers/crypto/hisilicon/qm.c cqc->w8 = QM_Q_DEPTH - 1; cqc 1251 drivers/crypto/hisilicon/qm.c cqc->dw3 = QM_MK_CQC_DW3_V2(4); cqc 1252 drivers/crypto/hisilicon/qm.c cqc->w8 = 0; cqc 1254 drivers/crypto/hisilicon/qm.c cqc->dw6 = 1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT; cqc 1258 drivers/crypto/hisilicon/qm.c kfree(cqc); cqc 1651 drivers/crypto/hisilicon/qm.c QM_INIT_BUF(qm, cqc, qm->qp_num); cqc 1661 drivers/crypto/hisilicon/qm.c qm->cqc, (unsigned long)qm->cqc_dma); cqc 139 drivers/crypto/hisilicon/qm.h struct qm_cqc *cqc; cqc 714 drivers/infiniband/hw/mlx5/cq.c void *cqc; cqc 762 drivers/infiniband/hw/mlx5/cq.c cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); cqc 763 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, log_page_size, cqc 791 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, cqe_comp_en, 1); cqc 792 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format); cqc 850 drivers/infiniband/hw/mlx5/cq.c void *cqc; cqc 879 drivers/infiniband/hw/mlx5/cq.c cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); cqc 880 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, log_page_size, cqc 922 drivers/infiniband/hw/mlx5/cq.c void *cqc; cqc 969 drivers/infiniband/hw/mlx5/cq.c cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context); cqc 970 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, cqe_sz, cqc 974 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); cqc 975 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, uar_page, index); cqc 976 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, c_eqn, eqn); cqc 977 drivers/infiniband/hw/mlx5/cq.c MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); cqc 979 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, oi, 1); cqc 1233 drivers/infiniband/hw/mlx5/cq.c void *cqc; cqc 1303 drivers/infiniband/hw/mlx5/cq.c cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); cqc 1305 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, log_page_size, cqc 1307 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, cqe_sz, cqc 1311 drivers/infiniband/hw/mlx5/cq.c MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries)); cqc 664 drivers/infiniband/hw/mlx5/devx.c void *cqc; cqc 667 drivers/infiniband/hw/mlx5/devx.c cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); cqc 668 drivers/infiniband/hw/mlx5/devx.c MLX5_SET(cqc, cqc, dbr_umem_valid, 1); cqc 3076 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c static int cq_get_mtt_addr(struct mlx4_cq_context *cqc) cqc 3078 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8; cqc 3081 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c static int cq_get_mtt_size(struct mlx4_cq_context *cqc) cqc 3083 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f; cqc 3084 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int page_shift = (cqc->log_page_size & 0x3f) + 12; cqc 3441 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c struct mlx4_cq_context *cqc = inbox->buf; cqc 3442 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz; cqc 3452 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt); cqc 3530 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c struct mlx4_cq_context *cqc = inbox->buf; cqc 3531 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz; cqc 3546 drivers/net/ethernet/mellanox/mlx4/resource_tracker.c err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt); cqc 93 drivers/net/ethernet/mellanox/mlx5/core/cq.c int eqn = MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), c_eqn); cqc 209 drivers/net/ethernet/mellanox/mlx5/core/cq.c void *cqc; cqc 212 drivers/net/ethernet/mellanox/mlx5/core/cq.c cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); cqc 213 drivers/net/ethernet/mellanox/mlx5/core/cq.c MLX5_SET(cqc, cqc, cq_period, cq_period); cqc 214 drivers/net/ethernet/mellanox/mlx5/core/cq.c MLX5_SET(cqc, cqc, cq_max_count, cq_max_count); cqc 359 drivers/net/ethernet/mellanox/mlx5/core/debugfs.c param = 1 << MLX5_GET(cqc, ctx, log_cq_size); cqc 362 drivers/net/ethernet/mellanox/mlx5/core/debugfs.c param = MLX5_GET(cqc, ctx, log_page_size); cqc 42 drivers/net/ethernet/mellanox/mlx5/core/en/health.c void *cqc; cqc 49 drivers/net/ethernet/mellanox/mlx5/core/en/health.c cqc = MLX5_ADDR_OF(query_cq_out, out, cq_context); cqc 50 drivers/net/ethernet/mellanox/mlx5/core/en/health.c hw_status = MLX5_GET(cqc, cqc, status); cqc 27 drivers/net/ethernet/mellanox/mlx5/core/en/params.h u32 cqc[MLX5_ST_SZ_DW(cqc)]; cqc 1547 drivers/net/ethernet/mellanox/mlx5/core/en_main.c err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, cqc 1604 drivers/net/ethernet/mellanox/mlx5/core/en_main.c void *cqc; cqc 1620 drivers/net/ethernet/mellanox/mlx5/core/en_main.c cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); cqc 1622 drivers/net/ethernet/mellanox/mlx5/core/en_main.c memcpy(cqc, param->cqc, sizeof(param->cqc)); cqc 1627 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); cqc 1628 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, c_eqn, eqn); cqc 1629 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); cqc 1630 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - cqc 1632 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); cqc 2231 drivers/net/ethernet/mellanox/mlx5/core/en_main.c void *cqc = param->cqc; cqc 2233 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); cqc 2235 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); cqc 2244 drivers/net/ethernet/mellanox/mlx5/core/en_main.c void *cqc = param->cqc; cqc 2256 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); cqc 2258 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); cqc 2259 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, cqe_comp_en, 1); cqc 2270 drivers/net/ethernet/mellanox/mlx5/core/en_main.c void *cqc = param->cqc; cqc 2272 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); cqc 2282 drivers/net/ethernet/mellanox/mlx5/core/en_main.c void *cqc = param->cqc; cqc 2284 drivers/net/ethernet/mellanox/mlx5/core/en_main.c MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); cqc 432 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c u32 temp_cqc[MLX5_ST_SZ_DW(cqc)] = {0}; cqc 438 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c void *cqc, *in; cqc 443 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c MLX5_SET(cqc, temp_cqc, log_cq_size, ilog2(cq_size)); cqc 472 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); cqc 473 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c MLX5_SET(cqc, cqc, log_cq_size, ilog2(cq_size)); cqc 474 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c MLX5_SET(cqc, cqc, c_eqn, eqn); cqc 475 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c MLX5_SET(cqc, cqc, uar_page, fdev->conn_res.uar->index); cqc 476 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c MLX5_SET(cqc, cqc, log_page_size, conn->cq.wq_ctrl.buf.page_shift - cqc 478 drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c MLX5_SET64(cqc, cqc, dbr_addr, conn->cq.wq_ctrl.db.dma); cqc 702 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c u32 temp_cqc[MLX5_ST_SZ_DW(cqc)] = {}; cqc 709 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c void *cqc, *in; cqc 719 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c MLX5_SET(cqc, temp_cqc, log_cq_size, ilog2(ncqe)); cqc 747 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); cqc 748 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c MLX5_SET(cqc, cqc, log_cq_size, ilog2(ncqe)); cqc 749 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c MLX5_SET(cqc, cqc, c_eqn, eqn); cqc 750 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c MLX5_SET(cqc, cqc, uar_page, uar->index); cqc 751 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - cqc 753 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); cqc 167 drivers/net/ethernet/mellanox/mlx5/core/wq.c void *cqc, struct mlx5_cqwq *wq, cqc 171 drivers/net/ethernet/mellanox/mlx5/core/wq.c u8 log_wq_stride = MLX5_GET(cqc, cqc, cqe_sz) == CQE_STRIDE_64 ? 6 : 7; cqc 172 drivers/net/ethernet/mellanox/mlx5/core/wq.c u8 log_wq_sz = MLX5_GET(cqc, cqc, log_cq_size); cqc 91 drivers/net/ethernet/mellanox/mlx5/core/wq.h void *cqc, struct mlx5_cqwq *wq, cqc 133 include/linux/mlx5/cq.h #define MLX5_MAX_CQ_PERIOD (BIT(__mlx5_bit_sz(cqc, cq_period)) - 1) cqc 134 include/linux/mlx5/cq.h #define MLX5_MAX_CQ_COUNT (BIT(__mlx5_bit_sz(cqc, cq_max_count)) - 1)