DCHUBP_CNTL 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE_2(DCHUBP_CNTL, DCHUBP_CNTL 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); DCHUBP_CNTL 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_WAIT(DCHUBP_CNTL, DCHUBP_CNTL 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCHUBP_CNTL, DCHUBP_CNTL 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCHUBP_CNTL, DCHUBP_CNTL 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCHUBP_CNTL, DCHUBP_CNTL 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); DCHUBP_CNTL 115 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en); DCHUBP_CNTL 1004 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET_3(DCHUBP_CNTL, DCHUBP_CNTL 1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); DCHUBP_CNTL 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h SRI(DCHUBP_CNTL, HUBP, id),\ DCHUBP_CNTL 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h uint32_t DCHUBP_CNTL; \ DCHUBP_CNTL 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); DCHUBP_CNTL 914 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE_2(DCHUBP_CNTL, DCHUBP_CNTL 919 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); DCHUBP_CNTL 928 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_WAIT(DCHUBP_CNTL, DCHUBP_CNTL 1034 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); DCHUBP_CNTL 1041 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); DCHUBP_CNTL 1202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET_3(DCHUBP_CNTL,