DCHUBBUB_ARB_SAT_LEVEL  618 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 	REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
DCHUBBUB_ARB_SAT_LEVEL  619 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c 			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
DCHUBBUB_ARB_SAT_LEVEL   46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 	SR(DCHUBBUB_ARB_SAT_LEVEL),\
DCHUBBUB_ARB_SAT_LEVEL  102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 	uint32_t DCHUBBUB_ARB_SAT_LEVEL;
DCHUBBUB_ARB_SAT_LEVEL  159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 		HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
DCHUBBUB_ARB_SAT_LEVEL  198 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h 		type DCHUBBUB_ARB_SAT_LEVEL;\
DCHUBBUB_ARB_SAT_LEVEL  587 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
DCHUBBUB_ARB_SAT_LEVEL  588 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c 			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
DCHUBBUB_ARB_SAT_LEVEL  501 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
DCHUBBUB_ARB_SAT_LEVEL  502 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);