cpt 71 arch/parisc/kernel/time.c unsigned long cpt = clocktick; cpt 82 arch/parisc/kernel/time.c next_tick += cpt; cpt 83 arch/parisc/kernel/time.c } while (next_tick - now > cpt); cpt 107 arch/parisc/kernel/time.c while (next_tick - now > cpt) cpt 108 arch/parisc/kernel/time.c next_tick += cpt; cpt 117 arch/parisc/kernel/time.c next_tick += cpt; cpt 96 arch/s390/include/asm/cio.h __u32 cpt : 1; cpt 24 drivers/crypto/cavium/cpt/cpt_common.h #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED) cpt 25 drivers/crypto/cavium/cpt/cpt_common.h #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER) cpt 26 drivers/crypto/cavium/cpt/cpt_common.h #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY) cpt 60 drivers/crypto/cavium/cpt/cptpf.h void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx); cpt 27 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask, cpt 33 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 36 drivers/crypto/cavium/cpt/cptpf_main.c coremask = (coremask << cpt->max_se_cores); cpt 39 drivers/crypto/cavium/cpt/cptpf_main.c grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); cpt 40 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), cpt 43 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); cpt 46 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, cpt 55 drivers/crypto/cavium/cpt/cptpf_main.c pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); cpt 56 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), cpt 64 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_enable_cores(struct cpt_device *cpt, u64 coremask, cpt 70 drivers/crypto/cavium/cpt/cptpf_main.c coremask = (coremask << cpt->max_se_cores); cpt 72 drivers/crypto/cavium/cpt/cptpf_main.c pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); cpt 73 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), cpt 78 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_configure_group(struct cpt_device *cpt, u8 grp, cpt 84 drivers/crypto/cavium/cpt/cptpf_main.c coremask = (coremask << cpt->max_se_cores); cpt 86 drivers/crypto/cavium/cpt/cptpf_main.c pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); cpt 87 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), cpt 92 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_disable_mbox_interrupts(struct cpt_device *cpt) cpt 95 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull); cpt 98 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_disable_ecc_interrupts(struct cpt_device *cpt) cpt 101 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull); cpt 104 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_disable_exec_interrupts(struct cpt_device *cpt) cpt 107 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull); cpt 110 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_disable_all_interrupts(struct cpt_device *cpt) cpt 112 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_mbox_interrupts(cpt); cpt 113 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_ecc_interrupts(cpt); cpt 114 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_exec_interrupts(cpt); cpt 117 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_enable_mbox_interrupts(struct cpt_device *cpt) cpt 120 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull); cpt 123 drivers/crypto/cavium/cpt/cptpf_main.c static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) cpt 127 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 153 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, cpt 161 drivers/crypto/cavium/cpt/cptpf_main.c static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) cpt 164 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 167 drivers/crypto/cavium/cpt/cptpf_main.c cpt->flags &= ~CPT_FLAG_DEVICE_READY; cpt 169 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_all_interrupts(cpt); cpt 172 drivers/crypto/cavium/cpt/cptpf_main.c if (mcode->num_cores > cpt->max_ae_cores) { cpt 178 drivers/crypto/cavium/cpt/cptpf_main.c if (cpt->next_group >= CPT_MAX_CORE_GROUPS) { cpt 183 drivers/crypto/cavium/cpt/cptpf_main.c mcode->group = cpt->next_group; cpt 186 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_cores(cpt, mcode->core_mask, AE_TYPES, cpt 189 drivers/crypto/cavium/cpt/cptpf_main.c ret = cpt_load_microcode(cpt, mcode); cpt 195 drivers/crypto/cavium/cpt/cptpf_main.c cpt->next_group++; cpt 197 drivers/crypto/cavium/cpt/cptpf_main.c cpt_configure_group(cpt, mcode->group, mcode->core_mask, cpt 200 drivers/crypto/cavium/cpt/cptpf_main.c cpt_enable_cores(cpt, mcode->core_mask, AE_TYPES); cpt 202 drivers/crypto/cavium/cpt/cptpf_main.c if (mcode->num_cores > cpt->max_se_cores) { cpt 207 drivers/crypto/cavium/cpt/cptpf_main.c if (cpt->next_group >= CPT_MAX_CORE_GROUPS) { cpt 212 drivers/crypto/cavium/cpt/cptpf_main.c mcode->group = cpt->next_group; cpt 215 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_cores(cpt, mcode->core_mask, SE_TYPES, cpt 218 drivers/crypto/cavium/cpt/cptpf_main.c ret = cpt_load_microcode(cpt, mcode); cpt 224 drivers/crypto/cavium/cpt/cptpf_main.c cpt->next_group++; cpt 226 drivers/crypto/cavium/cpt/cptpf_main.c cpt_configure_group(cpt, mcode->group, mcode->core_mask, cpt 229 drivers/crypto/cavium/cpt/cptpf_main.c cpt_enable_cores(cpt, mcode->core_mask, SE_TYPES); cpt 233 drivers/crypto/cavium/cpt/cptpf_main.c cpt_enable_mbox_interrupts(cpt); cpt 234 drivers/crypto/cavium/cpt/cptpf_main.c cpt->flags |= CPT_FLAG_DEVICE_READY; cpt 240 drivers/crypto/cavium/cpt/cptpf_main.c cpt_enable_mbox_interrupts(cpt); cpt 252 drivers/crypto/cavium/cpt/cptpf_main.c static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae) cpt 255 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 265 drivers/crypto/cavium/cpt/cptpf_main.c mcode = &cpt->mcode[cpt->next_mc_idx]; cpt 278 drivers/crypto/cavium/cpt/cptpf_main.c mcode->code = dma_alloc_coherent(&cpt->pdev->dev, mcode->code_size, cpt 302 drivers/crypto/cavium/cpt/cptpf_main.c ret = do_cpt_init(cpt, mcode); cpt 310 drivers/crypto/cavium/cpt/cptpf_main.c cpt->next_mc_idx++; cpt 318 drivers/crypto/cavium/cpt/cptpf_main.c static int cpt_ucode_load(struct cpt_device *cpt) cpt 321 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 323 drivers/crypto/cavium/cpt/cptpf_main.c ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-ae.out", true); cpt 328 drivers/crypto/cavium/cpt/cptpf_main.c ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-se.out", false); cpt 339 drivers/crypto/cavium/cpt/cptpf_main.c struct cpt_device *cpt = (struct cpt_device *)cpt_irq; cpt 341 drivers/crypto/cavium/cpt/cptpf_main.c cpt_mbox_intr_handler(cpt, 0); cpt 346 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_reset(struct cpt_device *cpt) cpt 348 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1); cpt 351 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_find_max_enabled_cores(struct cpt_device *cpt) cpt 355 drivers/crypto/cavium/cpt/cptpf_main.c pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0)); cpt 356 drivers/crypto/cavium/cpt/cptpf_main.c cpt->max_se_cores = pf_cnsts.s.se; cpt 357 drivers/crypto/cavium/cpt/cptpf_main.c cpt->max_ae_cores = pf_cnsts.s.ae; cpt 360 drivers/crypto/cavium/cpt/cptpf_main.c static u32 cpt_check_bist_status(struct cpt_device *cpt) cpt 364 drivers/crypto/cavium/cpt/cptpf_main.c bist_sts.u = cpt_read_csr64(cpt->reg_base, cpt 370 drivers/crypto/cavium/cpt/cptpf_main.c static u64 cpt_check_exe_bist_status(struct cpt_device *cpt) cpt 374 drivers/crypto/cavium/cpt/cptpf_main.c bist_sts.u = cpt_read_csr64(cpt->reg_base, cpt 380 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_disable_all_cores(struct cpt_device *cpt) cpt 383 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 387 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0); cpt 391 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); cpt 394 drivers/crypto/cavium/cpt/cptpf_main.c grp = cpt_read_csr64(cpt->reg_base, cpt 402 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0); cpt 410 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_unload_microcode(struct cpt_device *cpt) cpt 416 drivers/crypto/cavium/cpt/cptpf_main.c struct microcode *mcode = &cpt->mcode[grp]; cpt 418 drivers/crypto/cavium/cpt/cptpf_main.c if (cpt->mcode[grp].code) cpt 419 drivers/crypto/cavium/cpt/cptpf_main.c dma_free_coherent(&cpt->pdev->dev, mcode->code_size, cpt 425 drivers/crypto/cavium/cpt/cptpf_main.c cpt_write_csr64(cpt->reg_base, cpt 429 drivers/crypto/cavium/cpt/cptpf_main.c static int cpt_device_init(struct cpt_device *cpt) cpt 432 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 435 drivers/crypto/cavium/cpt/cptpf_main.c cpt_reset(cpt); cpt 439 drivers/crypto/cavium/cpt/cptpf_main.c bist = (u64)cpt_check_bist_status(cpt); cpt 445 drivers/crypto/cavium/cpt/cptpf_main.c bist = cpt_check_exe_bist_status(cpt); cpt 453 drivers/crypto/cavium/cpt/cptpf_main.c cpt_find_max_enabled_cores(cpt); cpt 455 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_all_cores(cpt); cpt 457 drivers/crypto/cavium/cpt/cptpf_main.c cpt->next_mc_idx = 0; cpt 458 drivers/crypto/cavium/cpt/cptpf_main.c cpt->next_group = 0; cpt 460 drivers/crypto/cavium/cpt/cptpf_main.c cpt->flags |= CPT_FLAG_DEVICE_READY; cpt 465 drivers/crypto/cavium/cpt/cptpf_main.c static int cpt_register_interrupts(struct cpt_device *cpt) cpt 468 drivers/crypto/cavium/cpt/cptpf_main.c struct device *dev = &cpt->pdev->dev; cpt 471 drivers/crypto/cavium/cpt/cptpf_main.c ret = pci_alloc_irq_vectors(cpt->pdev, CPT_PF_MSIX_VECTORS, cpt 474 drivers/crypto/cavium/cpt/cptpf_main.c dev_err(&cpt->pdev->dev, "Request for #%d msix vectors failed\n", cpt 480 drivers/crypto/cavium/cpt/cptpf_main.c ret = request_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)), cpt 481 drivers/crypto/cavium/cpt/cptpf_main.c cpt_mbx0_intr_handler, 0, "CPT Mbox0", cpt); cpt 486 drivers/crypto/cavium/cpt/cptpf_main.c cpt_enable_mbox_interrupts(cpt); cpt 491 drivers/crypto/cavium/cpt/cptpf_main.c pci_disable_msix(cpt->pdev); cpt 495 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_unregister_interrupts(struct cpt_device *cpt) cpt 497 drivers/crypto/cavium/cpt/cptpf_main.c free_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)), cpt); cpt 498 drivers/crypto/cavium/cpt/cptpf_main.c pci_disable_msix(cpt->pdev); cpt 501 drivers/crypto/cavium/cpt/cptpf_main.c static int cpt_sriov_init(struct cpt_device *cpt, int num_vfs) cpt 506 drivers/crypto/cavium/cpt/cptpf_main.c struct pci_dev *pdev = cpt->pdev; cpt 514 drivers/crypto/cavium/cpt/cptpf_main.c cpt->num_vf_en = num_vfs; /* User requested VFs */ cpt 516 drivers/crypto/cavium/cpt/cptpf_main.c if (total_vf_cnt < cpt->num_vf_en) cpt 517 drivers/crypto/cavium/cpt/cptpf_main.c cpt->num_vf_en = total_vf_cnt; cpt 523 drivers/crypto/cavium/cpt/cptpf_main.c err = pci_enable_sriov(pdev, cpt->num_vf_en); cpt 526 drivers/crypto/cavium/cpt/cptpf_main.c cpt->num_vf_en); cpt 527 drivers/crypto/cavium/cpt/cptpf_main.c cpt->num_vf_en = 0; cpt 534 drivers/crypto/cavium/cpt/cptpf_main.c cpt->num_vf_en); cpt 536 drivers/crypto/cavium/cpt/cptpf_main.c cpt->flags |= CPT_FLAG_SRIOV_ENABLED; cpt 544 drivers/crypto/cavium/cpt/cptpf_main.c struct cpt_device *cpt; cpt 553 drivers/crypto/cavium/cpt/cptpf_main.c cpt = devm_kzalloc(dev, sizeof(*cpt), GFP_KERNEL); cpt 554 drivers/crypto/cavium/cpt/cptpf_main.c if (!cpt) cpt 557 drivers/crypto/cavium/cpt/cptpf_main.c pci_set_drvdata(pdev, cpt); cpt 558 drivers/crypto/cavium/cpt/cptpf_main.c cpt->pdev = pdev; cpt 585 drivers/crypto/cavium/cpt/cptpf_main.c cpt->reg_base = pcim_iomap(pdev, 0, 0); cpt 586 drivers/crypto/cavium/cpt/cptpf_main.c if (!cpt->reg_base) { cpt 593 drivers/crypto/cavium/cpt/cptpf_main.c cpt_device_init(cpt); cpt 596 drivers/crypto/cavium/cpt/cptpf_main.c err = cpt_register_interrupts(cpt); cpt 600 drivers/crypto/cavium/cpt/cptpf_main.c err = cpt_ucode_load(cpt); cpt 605 drivers/crypto/cavium/cpt/cptpf_main.c err = cpt_sriov_init(cpt, num_vfs); cpt 612 drivers/crypto/cavium/cpt/cptpf_main.c cpt_unregister_interrupts(cpt); cpt 623 drivers/crypto/cavium/cpt/cptpf_main.c struct cpt_device *cpt = pci_get_drvdata(pdev); cpt 626 drivers/crypto/cavium/cpt/cptpf_main.c cpt_disable_all_cores(cpt); cpt 628 drivers/crypto/cavium/cpt/cptpf_main.c cpt_unload_microcode(cpt); cpt 629 drivers/crypto/cavium/cpt/cptpf_main.c cpt_unregister_interrupts(cpt); cpt 638 drivers/crypto/cavium/cpt/cptpf_main.c struct cpt_device *cpt = pci_get_drvdata(pdev); cpt 640 drivers/crypto/cavium/cpt/cptpf_main.c if (!cpt) cpt 646 drivers/crypto/cavium/cpt/cptpf_main.c cpt_unregister_interrupts(cpt); cpt 8 drivers/crypto/cavium/cpt/cptpf_mbox.c static void cpt_send_msg_to_vf(struct cpt_device *cpt, int vf, cpt 12 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1), cpt 14 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0), mbx->msg); cpt 20 drivers/crypto/cavium/cpt/cptpf_mbox.c static void cpt_mbox_send_ack(struct cpt_device *cpt, int vf, cpt 25 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_send_msg_to_vf(cpt, vf, mbx); cpt 28 drivers/crypto/cavium/cpt/cptpf_mbox.c static void cpt_clear_mbox_intr(struct cpt_device *cpt, u32 vf) cpt 31 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0), (1 << vf)); cpt 37 drivers/crypto/cavium/cpt/cptpf_mbox.c static void cpt_cfg_qlen_for_vf(struct cpt_device *cpt, int vf, u32 size) cpt 41 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); cpt 44 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); cpt 50 drivers/crypto/cavium/cpt/cptpf_mbox.c static void cpt_cfg_vq_priority(struct cpt_device *cpt, int vf, u32 pri) cpt 54 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); cpt 56 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u); cpt 59 drivers/crypto/cavium/cpt/cptpf_mbox.c static int cpt_bind_vq_to_grp(struct cpt_device *cpt, u8 q, u8 grp) cpt 61 drivers/crypto/cavium/cpt/cptpf_mbox.c struct microcode *mcode = cpt->mcode; cpt 63 drivers/crypto/cavium/cpt/cptpf_mbox.c struct device *dev = &cpt->pdev->dev; cpt 73 drivers/crypto/cavium/cpt/cptpf_mbox.c if (grp >= cpt->next_mc_idx) { cpt 77 drivers/crypto/cavium/cpt/cptpf_mbox.c pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q)); cpt 79 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u); cpt 86 drivers/crypto/cavium/cpt/cptpf_mbox.c static void cpt_handle_mbox_intr(struct cpt_device *cpt, int vf) cpt 88 drivers/crypto/cavium/cpt/cptpf_mbox.c struct cpt_vf_info *vfx = &cpt->vfinfo[vf]; cpt 91 drivers/crypto/cavium/cpt/cptpf_mbox.c struct device *dev = &cpt->pdev->dev; cpt 96 drivers/crypto/cavium/cpt/cptpf_mbox.c mbx.msg = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0)); cpt 97 drivers/crypto/cavium/cpt/cptpf_mbox.c mbx.data = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1)); cpt 103 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_mbox_send_ack(cpt, vf, &mbx); cpt 108 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_send_msg_to_vf(cpt, vf, &mbx); cpt 114 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_mbox_send_ack(cpt, vf, &mbx); cpt 118 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_cfg_qlen_for_vf(cpt, vf, vfx->qlen); cpt 119 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_mbox_send_ack(cpt, vf, &mbx); cpt 122 drivers/crypto/cavium/cpt/cptpf_mbox.c vftype = cpt_bind_vq_to_grp(cpt, vf, (u8)mbx.data); cpt 131 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_send_msg_to_vf(cpt, vf, &mbx); cpt 136 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_cfg_vq_priority(cpt, vf, vfx->priority); cpt 137 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_mbox_send_ack(cpt, vf, &mbx); cpt 140 drivers/crypto/cavium/cpt/cptpf_mbox.c dev_err(&cpt->pdev->dev, "Invalid msg from VF%d, msg 0x%llx\n", cpt 146 drivers/crypto/cavium/cpt/cptpf_mbox.c void cpt_mbox_intr_handler (struct cpt_device *cpt, int mbx) cpt 151 drivers/crypto/cavium/cpt/cptpf_mbox.c intr = cpt_read_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0)); cpt 152 drivers/crypto/cavium/cpt/cptpf_mbox.c dev_dbg(&cpt->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr); cpt 155 drivers/crypto/cavium/cpt/cptpf_mbox.c dev_dbg(&cpt->pdev->dev, "Intr from VF %d\n", vf); cpt 156 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_handle_mbox_intr(cpt, vf); cpt 157 drivers/crypto/cavium/cpt/cptpf_mbox.c cpt_clear_mbox_intr(cpt, vf); cpt 1438 drivers/media/dvb-frontends/stv0367.c int cpt = 0; cpt 1441 drivers/media/dvb-frontends/stv0367.c while (cpt < 10) { cpt 1448 drivers/media/dvb-frontends/stv0367.c cpt++; cpt 1599 drivers/media/dvb-frontends/stv0367.c int abc = 0, def = 0, cpt = 0; cpt 1602 drivers/media/dvb-frontends/stv0367.c (cpt < 400)) || ((Errors == 0) && (cpt < 400))) { cpt 1609 drivers/media/dvb-frontends/stv0367.c cpt++; cpt 805 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c unsigned int v, addr, bpt, cpt; cpt 815 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c cpt = v & 0xff; cpt 816 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c if (!cpt) cpt 819 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c v = (adap->params.vpd.cclk * 1000) / cpt; cpt 3038 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; cpt 3044 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c for (cpt = 1; cpt <= 255; cpt++) { cpt 3045 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c tps = clk / cpt; cpt 3052 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c selected_cpt = cpt; cpt 10263 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int v, addr, bpt, cpt; cpt 10271 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c cpt = v & 0xff; cpt 10272 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c if (!cpt) { cpt 10275 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ cpt 741 drivers/net/ethernet/marvell/octeontx2/af/rvu.c goto cpt; cpt 759 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cpt: cpt 158 drivers/s390/cio/device_status.c cdev_irb->esw.esw0.erw.cpt = irb->esw.esw0.erw.cpt; cpt 684 tools/perf/builtin-kmem.c const char *cpt; cpt 690 tools/perf/builtin-kmem.c cpt = gfp_compact_table[i].compact; cpt 691 tools/perf/builtin-kmem.c new = realloc(new_flags, len + strlen(cpt) + 2); cpt 701 tools/perf/builtin-kmem.c strcpy(new_flags, cpt); cpt 704 tools/perf/builtin-kmem.c strcat(new_flags, cpt); cpt 708 tools/perf/builtin-kmem.c len += strlen(cpt);