DCFE_MEM_PWR_STATUS  201 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);
DCFE_MEM_PWR_STATUS 1155 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		if (REG(DCFE_MEM_PWR_STATUS)) {
DCFE_MEM_PWR_STATUS 1156 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_GET(DCFE_MEM_PWR_STATUS,
DCFE_MEM_PWR_STATUS  104 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
DCFE_MEM_PWR_STATUS  109 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
DCFE_MEM_PWR_STATUS  201 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
DCFE_MEM_PWR_STATUS  204 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
DCFE_MEM_PWR_STATUS  433 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t DCFE_MEM_PWR_STATUS;