DCFE_MEM_PWR_CTRL  179 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	if (REG(DCFE_MEM_PWR_CTRL))
DCFE_MEM_PWR_CTRL  180 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
DCFE_MEM_PWR_CTRL  211 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	if (REG(DCFE_MEM_PWR_CTRL))
DCFE_MEM_PWR_CTRL  212 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
DCFE_MEM_PWR_CTRL   58 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
DCFE_MEM_PWR_CTRL   62 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
DCFE_MEM_PWR_CTRL  108 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
DCFE_MEM_PWR_CTRL  213 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	uint32_t DCFE_MEM_PWR_CTRL;
DCFE_MEM_PWR_CTRL  197 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	if (REG(DCFE_MEM_PWR_CTRL)) {
DCFE_MEM_PWR_CTRL  198 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);
DCFE_MEM_PWR_CTRL  199 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
DCFE_MEM_PWR_CTRL  231 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	if (REG(DCFE_MEM_PWR_CTRL))
DCFE_MEM_PWR_CTRL  232 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
DCFE_MEM_PWR_CTRL 1147 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	if (REG(DCFE_MEM_PWR_CTRL))
DCFE_MEM_PWR_CTRL 1148 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_PWR_CTRL,
DCFE_MEM_PWR_CTRL 1201 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	if (REG(DCFE_MEM_PWR_CTRL))
DCFE_MEM_PWR_CTRL 1202 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_PWR_CTRL,
DCFE_MEM_PWR_CTRL 1305 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 	if (REG(DCFE_MEM_PWR_CTRL))
DCFE_MEM_PWR_CTRL 1306 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
DCFE_MEM_PWR_CTRL  103 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
DCFE_MEM_PWR_CTRL  108 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
DCFE_MEM_PWR_CTRL  200 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
DCFE_MEM_PWR_CTRL  202 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
DCFE_MEM_PWR_CTRL  203 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
DCFE_MEM_PWR_CTRL  432 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t DCFE_MEM_PWR_CTRL;