DCFE_MEM_LIGHT_SLEEP_CNTL 1151 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
DCFE_MEM_LIGHT_SLEEP_CNTL 1164 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 			REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
DCFE_MEM_LIGHT_SLEEP_CNTL 1205 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
DCFE_MEM_LIGHT_SLEEP_CNTL 1310 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c 		REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
DCFE_MEM_LIGHT_SLEEP_CNTL   99 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
DCFE_MEM_LIGHT_SLEEP_CNTL  194 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
DCFE_MEM_LIGHT_SLEEP_CNTL  195 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
DCFE_MEM_LIGHT_SLEEP_CNTL  196 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
DCFE_MEM_LIGHT_SLEEP_CNTL  401 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h 	uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;