cppr 503 arch/powerpc/include/asm/kvm_host.h u8 cppr; cppr 792 arch/powerpc/include/asm/kvm_ppc.h int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr); cppr 237 arch/powerpc/include/asm/opal.h int64_t opal_int_set_cppr(uint8_t cppr); cppr 131 arch/powerpc/include/asm/xics.h static inline void xics_set_base_cppr(unsigned char cppr) cppr 140 arch/powerpc/include/asm/xics.h os_cppr->stack[0] = cppr; cppr 3746 arch/powerpc/kvm/book3s_hv.c vcpu->arch.xive_saved_state.cppr; cppr 43 arch/powerpc/kvm/book3s_hv_builtin.c int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr); cppr 631 arch/powerpc/kvm/book3s_hv_builtin.c int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) cppr 637 arch/powerpc/kvm/book3s_hv_builtin.c return xive_rm_h_cppr(vcpu, cppr); cppr 640 arch/powerpc/kvm/book3s_hv_builtin.c return __xive_vm_h_cppr(vcpu, cppr); cppr 642 arch/powerpc/kvm/book3s_hv_builtin.c return xics_rm_h_cppr(vcpu, cppr); cppr 189 arch/powerpc/kvm/book3s_hv_rm_xics.c new.out_ee = (new.xisr && (new.pending_pri < new.cppr)); cppr 258 arch/powerpc/kvm/book3s_hv_rm_xics.c success = new_state.cppr > priority && cppr 455 arch/powerpc/kvm/book3s_hv_rm_xics.c new_state.cppr = new_cppr; cppr 513 arch/powerpc/kvm/book3s_hv_rm_xics.c xirr = old_state.xisr | (((u32)old_state.cppr) << 24); cppr 516 arch/powerpc/kvm/book3s_hv_rm_xics.c new_state.cppr = new_state.pending_pri; cppr 585 arch/powerpc/kvm/book3s_hv_rm_xics.c if (mfrr < new_state.cppr) { cppr 615 arch/powerpc/kvm/book3s_hv_rm_xics.c int xics_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) cppr 632 arch/powerpc/kvm/book3s_hv_rm_xics.c if (cppr > icp->state.cppr) { cppr 633 arch/powerpc/kvm/book3s_hv_rm_xics.c icp_rm_down_cppr(xics, icp, cppr); cppr 635 arch/powerpc/kvm/book3s_hv_rm_xics.c } else if (cppr == icp->state.cppr) cppr 655 arch/powerpc/kvm/book3s_hv_rm_xics.c new_state.cppr = cppr; cppr 657 arch/powerpc/kvm/book3s_hv_rm_xics.c if (cppr <= new_state.pending_pri) { cppr 279 arch/powerpc/kvm/book3s_xics.c new.out_ee = (new.xisr && (new.pending_pri < new.cppr)); cppr 288 arch/powerpc/kvm/book3s_xics.c old.cppr, old.mfrr, old.pending_pri, old.xisr, cppr 291 arch/powerpc/kvm/book3s_xics.c new.cppr, new.mfrr, new.pending_pri, new.xisr, cppr 351 arch/powerpc/kvm/book3s_xics.c success = new_state.cppr > priority && cppr 552 arch/powerpc/kvm/book3s_xics.c new_state.cppr = new_cppr; cppr 605 arch/powerpc/kvm/book3s_xics.c xirr = old_state.xisr | (((u32)old_state.cppr) << 24); cppr 608 arch/powerpc/kvm/book3s_xics.c new_state.cppr = new_state.pending_pri; cppr 678 arch/powerpc/kvm/book3s_xics.c if (mfrr < new_state.cppr) { cppr 716 arch/powerpc/kvm/book3s_xics.c kvmppc_set_gpr(vcpu, 4, ((u32)state.cppr << 24) | state.xisr); cppr 721 arch/powerpc/kvm/book3s_xics.c static noinline void kvmppc_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) cppr 728 arch/powerpc/kvm/book3s_xics.c XICS_DBG("h_cppr vcpu %d cppr %#lx\n", vcpu->vcpu_id, cppr); cppr 737 arch/powerpc/kvm/book3s_xics.c if (cppr > icp->state.cppr) cppr 738 arch/powerpc/kvm/book3s_xics.c icp_down_cppr(xics, icp, cppr); cppr 739 arch/powerpc/kvm/book3s_xics.c else if (cppr == icp->state.cppr) cppr 759 arch/powerpc/kvm/book3s_xics.c new_state.cppr = cppr; cppr 761 arch/powerpc/kvm/book3s_xics.c if (cppr <= new_state.pending_pri) { cppr 974 arch/powerpc/kvm/book3s_xics.c state.pending_pri, state.cppr, state.mfrr, cppr 1104 arch/powerpc/kvm/book3s_xics.c return ((u64)state.cppr << KVM_REG_PPC_ICP_CPPR_SHIFT) | cppr 1116 arch/powerpc/kvm/book3s_xics.c u8 cppr, mfrr, pending_pri; cppr 1124 arch/powerpc/kvm/book3s_xics.c cppr = icpval >> KVM_REG_PPC_ICP_CPPR_SHIFT; cppr 1135 arch/powerpc/kvm/book3s_xics.c if (pending_pri != mfrr || pending_pri >= cppr) cppr 1138 arch/powerpc/kvm/book3s_xics.c if (pending_pri >= mfrr || pending_pri >= cppr) cppr 1146 arch/powerpc/kvm/book3s_xics.c new_state.cppr = cppr; cppr 56 arch/powerpc/kvm/book3s_xics.h u8 cppr; cppr 148 arch/powerpc/kvm/book3s_xics.h extern int xics_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr); cppr 832 arch/powerpc/kvm/book3s_xive.c return (u64)xc->cppr << KVM_REG_PPC_ICP_CPPR_SHIFT | cppr 841 arch/powerpc/kvm/book3s_xive.c u8 cppr, mfrr; cppr 848 arch/powerpc/kvm/book3s_xive.c cppr = icpval >> KVM_REG_PPC_ICP_CPPR_SHIFT; cppr 854 arch/powerpc/kvm/book3s_xive.c xc->server_num, cppr, mfrr, xisr); cppr 865 arch/powerpc/kvm/book3s_xive.c vcpu->arch.xive_saved_state.cppr = cppr; cppr 866 arch/powerpc/kvm/book3s_xive.c xc->hw_cppr = xc->cppr = cppr; cppr 875 arch/powerpc/kvm/book3s_xive.c if (mfrr < cppr) cppr 2112 arch/powerpc/kvm/book3s_xive.c xc->server_num, xc->cppr, xc->hw_cppr, cppr 167 arch/powerpc/kvm/book3s_xive.h uint8_t cppr; /* guest CPPR */ cppr 275 arch/powerpc/kvm/book3s_xive.h extern int xive_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr); cppr 282 arch/powerpc/kvm/book3s_xive.h extern int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr); cppr 1157 arch/powerpc/kvm/book3s_xive_native.c vcpu->arch.xive_saved_state.cppr, cppr 1224 arch/powerpc/kvm/book3s_xive_native.c vcpu->arch.xive_saved_state.cppr, cppr 16 arch/powerpc/kvm/book3s_xive_template.c u8 cppr; cppr 38 arch/powerpc/kvm/book3s_xive_template.c cppr = ack & 0xff; cppr 39 arch/powerpc/kvm/book3s_xive_template.c if (cppr < 8) cppr 40 arch/powerpc/kvm/book3s_xive_template.c xc->pending |= 1 << cppr; cppr 44 arch/powerpc/kvm/book3s_xive_template.c if (cppr >= xc->hw_cppr) cppr 46 arch/powerpc/kvm/book3s_xive_template.c smp_processor_id(), cppr, xc->hw_cppr); cppr 54 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = cppr; cppr 131 arch/powerpc/kvm/book3s_xive_template.c if (prio >= xc->cppr || prio > 7) { cppr 132 arch/powerpc/kvm/book3s_xive_template.c if (xc->mfrr < xc->cppr) { cppr 216 arch/powerpc/kvm/book3s_xive_template.c if (prio >= xc->mfrr && xc->mfrr < xc->cppr) { cppr 254 arch/powerpc/kvm/book3s_xive_template.c xc->cppr = prio; cppr 261 arch/powerpc/kvm/book3s_xive_template.c if (xc->cppr != xc->hw_cppr) { cppr 262 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = xc->cppr; cppr 263 arch/powerpc/kvm/book3s_xive_template.c __x_writeb(xc->cppr, __x_tima + TM_QW1_OS + TM_CPPR); cppr 283 arch/powerpc/kvm/book3s_xive_template.c xc->pending, xc->hw_cppr, xc->cppr); cppr 286 arch/powerpc/kvm/book3s_xive_template.c old_cppr = xive_prio_to_guest(xc->cppr); cppr 292 arch/powerpc/kvm/book3s_xive_template.c hirq, xc->hw_cppr, xc->cppr); cppr 350 arch/powerpc/kvm/book3s_xive_template.c vcpu->arch.regs.gpr[4] = hirq | (xc->cppr << 24); cppr 379 arch/powerpc/kvm/book3s_xive_template.c for (prio = xc->cppr; prio < KVMPPC_XIVE_Q_COUNT; prio++) { cppr 439 arch/powerpc/kvm/book3s_xive_template.c X_STATIC int GLUE(X_PFX,h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr) cppr 445 arch/powerpc/kvm/book3s_xive_template.c pr_devel("H_CPPR(cppr=%ld)\n", cppr); cppr 450 arch/powerpc/kvm/book3s_xive_template.c cppr = xive_prio_from_guest(cppr); cppr 453 arch/powerpc/kvm/book3s_xive_template.c old_cppr = xc->cppr; cppr 454 arch/powerpc/kvm/book3s_xive_template.c xc->cppr = cppr; cppr 462 arch/powerpc/kvm/book3s_xive_template.c if (cppr > old_cppr) { cppr 492 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = cppr; cppr 493 arch/powerpc/kvm/book3s_xive_template.c __x_writeb(cppr, __x_tima + TM_QW1_OS + TM_CPPR); cppr 514 arch/powerpc/kvm/book3s_xive_template.c xc->cppr = xive_prio_from_guest(new_cppr); cppr 597 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = xc->cppr; cppr 598 arch/powerpc/kvm/book3s_xive_template.c __x_writeb(xc->cppr, __x_tima + TM_QW1_OS + TM_CPPR); cppr 634 arch/powerpc/kvm/book3s_xive_template.c if (mfrr < xc->cppr) cppr 20 arch/powerpc/sysdev/xics/icp-hv.c static inline unsigned int icp_hv_get_xirr(unsigned char cppr) cppr 26 arch/powerpc/sysdev/xics/icp-hv.c rc = plpar_hcall(H_XIRR, retbuf, cppr); cppr 31 arch/powerpc/sysdev/xics/icp-hv.c __func__, cppr, rc); cppr 127 arch/powerpc/sysdev/xics/icp-hv.c static void icp_hv_set_cpu_priority(unsigned char cppr) cppr 129 arch/powerpc/sysdev/xics/icp-hv.c xics_set_base_cppr(cppr); cppr 130 arch/powerpc/sysdev/xics/icp-hv.c icp_hv_set_cppr(cppr); cppr 79 arch/powerpc/sysdev/xics/icp-native.c static void icp_native_set_cpu_priority(unsigned char cppr) cppr 81 arch/powerpc/sysdev/xics/icp-native.c xics_set_base_cppr(cppr); cppr 82 arch/powerpc/sysdev/xics/icp-native.c icp_native_set_cppr(cppr); cppr 88 arch/powerpc/sysdev/xics/icp-opal.c static void icp_opal_set_cpu_priority(unsigned char cppr) cppr 97 arch/powerpc/sysdev/xics/icp-opal.c if (cppr >= DEFAULT_PRIORITY) cppr 98 arch/powerpc/sysdev/xics/icp-opal.c cppr = LOWEST_PRIORITY; cppr 100 arch/powerpc/sysdev/xics/icp-opal.c xics_set_base_cppr(cppr); cppr 101 arch/powerpc/sysdev/xics/icp-opal.c opal_int_set_cppr(cppr); cppr 182 arch/powerpc/sysdev/xive/common.c if (prio != xc->cppr) { cppr 184 arch/powerpc/sysdev/xive/common.c xc->cppr = prio; cppr 244 arch/powerpc/sysdev/xive/common.c xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); cppr 1366 arch/powerpc/sysdev/xive/common.c xc->cppr = 0xff; cppr 1459 arch/powerpc/sysdev/xive/common.c xc->cppr = 0; cppr 1466 arch/powerpc/sysdev/xive/common.c xc->cppr = 0xff; cppr 1489 arch/powerpc/sysdev/xive/common.c xc->cppr = 0; cppr 342 arch/powerpc/sysdev/xive/native.c u8 he, cppr; cppr 355 arch/powerpc/sysdev/xive/native.c cppr = ack & 0xff; cppr 361 arch/powerpc/sysdev/xive/native.c if (cppr == 0xff) cppr 364 arch/powerpc/sysdev/xive/native.c xc->pending_prio |= 1 << cppr; cppr 370 arch/powerpc/sysdev/xive/native.c if (cppr >= xc->cppr) cppr 372 arch/powerpc/sysdev/xive/native.c smp_processor_id(), cppr, xc->cppr); cppr 375 arch/powerpc/sysdev/xive/native.c xc->cppr = cppr; cppr 582 arch/powerpc/sysdev/xive/spapr.c u8 nsr, cppr; cppr 601 arch/powerpc/sysdev/xive/spapr.c cppr = ack & 0xff; cppr 605 arch/powerpc/sysdev/xive/spapr.c if (cppr == 0xff) cppr 608 arch/powerpc/sysdev/xive/spapr.c xc->pending_prio |= 1 << cppr; cppr 614 arch/powerpc/sysdev/xive/spapr.c if (cppr >= xc->cppr) cppr 616 arch/powerpc/sysdev/xive/spapr.c smp_processor_id(), cppr, xc->cppr); cppr 619 arch/powerpc/sysdev/xive/spapr.c xc->cppr = cppr; cppr 36 arch/powerpc/sysdev/xive/xive-internal.h u8 cppr;