DCE_BASE           46 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
DCE_BASE           45 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
DCE_BASE          160 drivers/gpu/drm/amd/display/dc/dm_services.h 		dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
DCE_BASE          163 drivers/gpu/drm/amd/display/dc/dm_services.h 		dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
DCE_BASE          166 drivers/gpu/drm/amd/display/dc/dm_services.h 		generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] +  mm##reg_name + inst_offset, \
DCE_BASE          170 drivers/gpu/drm/amd/display/dc/dm_services.h 		generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
DCE_BASE           48 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE DCE_BASE			= { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
DCE_BASE           51 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE DCE_BASE            ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } },