cp_mqd_base_addr_hi 3032 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
cp_mqd_base_addr_hi 3117 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
cp_mqd_base_addr_hi 3314 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
cp_mqd_base_addr_hi 3436 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	       mqd->cp_mqd_base_addr_hi);
cp_mqd_base_addr_hi 2838 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 cp_mqd_base_addr_hi;
cp_mqd_base_addr_hi 2955 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
cp_mqd_base_addr_hi 4496 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
cp_mqd_base_addr_hi 3475 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
cp_mqd_base_addr_hi 3596 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	       mqd->cp_mqd_base_addr_hi);
cp_mqd_base_addr_hi  116 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
cp_mqd_base_addr_hi  128 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
cp_mqd_base_addr_hi  147 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
cp_mqd_base_addr_hi  116 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
cp_mqd_base_addr_hi   80 drivers/gpu/drm/amd/include/cik_structs.h 	uint32_t cp_mqd_base_addr_hi;
cp_mqd_base_addr_hi  158 drivers/gpu/drm/amd/include/v10_structs.h 	uint32_t cp_mqd_base_addr_hi; // offset: 129  (0x81)
cp_mqd_base_addr_hi  806 drivers/gpu/drm/amd/include/v10_structs.h 	uint32_t cp_mqd_base_addr_hi;
cp_mqd_base_addr_hi  289 drivers/gpu/drm/amd/include/v9_structs.h 	uint32_t cp_mqd_base_addr_hi;
cp_mqd_base_addr_hi  289 drivers/gpu/drm/amd/include/vi_structs.h 	uint32_t cp_mqd_base_addr_hi;
cp_mqd_base_addr_hi 4449 drivers/gpu/drm/radeon/cik.c 	u32 cp_mqd_base_addr_hi;
cp_mqd_base_addr_hi 4656 drivers/gpu/drm/radeon/cik.c 		mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
cp_mqd_base_addr_hi 4658 drivers/gpu/drm/radeon/cik.c 		WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);