cp_mqd_base_addr 3031 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
cp_mqd_base_addr 3116 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
cp_mqd_base_addr 2837 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 cp_mqd_base_addr;
cp_mqd_base_addr  157 drivers/gpu/drm/amd/include/v10_structs.h 	uint32_t cp_mqd_base_addr; // offset: 128  (0x80)
cp_mqd_base_addr 4448 drivers/gpu/drm/radeon/cik.c 	u32 cp_mqd_base_addr;
cp_mqd_base_addr 4655 drivers/gpu/drm/radeon/cik.c 		mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
cp_mqd_base_addr 4657 drivers/gpu/drm/radeon/cik.c 		WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);