cp_m1p2 7033 drivers/gpu/drm/radeon/cik.c u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3; cp_m1p2 7068 drivers/gpu/drm/radeon/cik.c cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; cp_m1p2 7092 drivers/gpu/drm/radeon/cik.c cp_m1p2 |= TIME_STAMP_INT_ENABLE; cp_m1p2 7095 drivers/gpu/drm/radeon/cik.c cp_m1p2 |= TIME_STAMP_INT_ENABLE; cp_m1p2 7135 drivers/gpu/drm/radeon/cik.c cp_m1p2 |= TIME_STAMP_INT_ENABLE; cp_m1p2 7138 drivers/gpu/drm/radeon/cik.c cp_m1p2 |= TIME_STAMP_INT_ENABLE; cp_m1p2 7239 drivers/gpu/drm/radeon/cik.c WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);