cp_m1p1          7033 drivers/gpu/drm/radeon/cik.c 	u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
cp_m1p1          7067 drivers/gpu/drm/radeon/cik.c 	cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
cp_m1p1          7089 drivers/gpu/drm/radeon/cik.c 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;
cp_m1p1          7132 drivers/gpu/drm/radeon/cik.c 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;
cp_m1p1          7238 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);