cp_m1p0          7033 drivers/gpu/drm/radeon/cik.c 	u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
cp_m1p0          7066 drivers/gpu/drm/radeon/cik.c 	cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
cp_m1p0          7086 drivers/gpu/drm/radeon/cik.c 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;
cp_m1p0          7129 drivers/gpu/drm/radeon/cik.c 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;
cp_m1p0          7237 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);