cp_int_cntl1     4495 drivers/gpu/drm/radeon/evergreen.c 	u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
cp_int_cntl1     4529 drivers/gpu/drm/radeon/evergreen.c 			cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
cp_int_cntl1     4563 drivers/gpu/drm/radeon/evergreen.c 		cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
cp_int_cntl1     6054 drivers/gpu/drm/radeon/si.c 	u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
cp_int_cntl1     6087 drivers/gpu/drm/radeon/si.c 		cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
cp_int_cntl1     6104 drivers/gpu/drm/radeon/si.c 	WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);