cp_int_cntl      4858 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	uint32_t cp_int_cntl, cp_int_cntl_reg;
cp_int_cntl      4879 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = RREG32(cp_int_cntl_reg);
cp_int_cntl      4880 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
cp_int_cntl      4882 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32(cp_int_cntl_reg, cp_int_cntl);
cp_int_cntl      4885 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = RREG32(cp_int_cntl_reg);
cp_int_cntl      4886 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
cp_int_cntl      4888 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		WREG32(cp_int_cntl_reg, cp_int_cntl);
cp_int_cntl      3239 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	u32 cp_int_cntl;
cp_int_cntl      3243 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      3244 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      3245 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      3248 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      3249 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      3250 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      3261 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	u32 cp_int_cntl;
cp_int_cntl      3265 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
cp_int_cntl      3266 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      3267 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
cp_int_cntl      3270 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
cp_int_cntl      3271 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      3272 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
cp_int_cntl      3278 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
cp_int_cntl      3279 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      3280 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
cp_int_cntl      3283 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
cp_int_cntl      3284 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      3285 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
cp_int_cntl      3302 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	u32 cp_int_cntl;
cp_int_cntl      3306 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      3307 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
cp_int_cntl      3308 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      3311 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      3312 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
cp_int_cntl      3313 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      3327 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	u32 cp_int_cntl;
cp_int_cntl      3331 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      3332 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
cp_int_cntl      3333 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      3336 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      3337 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
cp_int_cntl      3338 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      4705 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 cp_int_cntl;
cp_int_cntl      4709 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      4710 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      4711 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      4714 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      4715 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
cp_int_cntl      4716 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      4779 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 cp_int_cntl;
cp_int_cntl      4783 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      4784 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
cp_int_cntl      4785 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      4788 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      4789 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
cp_int_cntl      4790 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      4804 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 cp_int_cntl;
cp_int_cntl      4808 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      4809 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
cp_int_cntl      4810 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      4813 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
cp_int_cntl      4814 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
cp_int_cntl      4815 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl      7032 drivers/gpu/drm/radeon/cik.c 	u32 cp_int_cntl;
cp_int_cntl      7052 drivers/gpu/drm/radeon/cik.c 	cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
cp_int_cntl      7054 drivers/gpu/drm/radeon/cik.c 	cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
cp_int_cntl      7078 drivers/gpu/drm/radeon/cik.c 		cp_int_cntl |= TIME_STAMP_INT_ENABLE;
cp_int_cntl      7232 drivers/gpu/drm/radeon/cik.c 	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
cp_int_cntl       217 drivers/gpu/drm/radeon/evergreen.c 				     int ring, u32 cp_int_cntl);
cp_int_cntl      4494 drivers/gpu/drm/radeon/evergreen.c 	u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
cp_int_cntl      4525 drivers/gpu/drm/radeon/evergreen.c 			cp_int_cntl |= TIME_STAMP_INT_ENABLE;
cp_int_cntl      4538 drivers/gpu/drm/radeon/evergreen.c 			cp_int_cntl |= RB_INT_ENABLE;
cp_int_cntl      4539 drivers/gpu/drm/radeon/evergreen.c 			cp_int_cntl |= TIME_STAMP_INT_ENABLE;
cp_int_cntl      4562 drivers/gpu/drm/radeon/evergreen.c 		cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
cp_int_cntl      4566 drivers/gpu/drm/radeon/evergreen.c 		WREG32(CP_INT_CNTL, cp_int_cntl);
cp_int_cntl      1393 drivers/gpu/drm/radeon/ni.c 			      int ring, u32 cp_int_cntl)
cp_int_cntl      1396 drivers/gpu/drm/radeon/ni.c 	WREG32(CP_INT_CNTL, cp_int_cntl);
cp_int_cntl      3766 drivers/gpu/drm/radeon/r600.c 	u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
cp_int_cntl      3824 drivers/gpu/drm/radeon/r600.c 		cp_int_cntl |= RB_INT_ENABLE;
cp_int_cntl      3825 drivers/gpu/drm/radeon/r600.c 		cp_int_cntl |= TIME_STAMP_INT_ENABLE;
cp_int_cntl      3876 drivers/gpu/drm/radeon/r600.c 	WREG32(CP_INT_CNTL, cp_int_cntl);
cp_int_cntl      6053 drivers/gpu/drm/radeon/si.c 	u32 cp_int_cntl;
cp_int_cntl      6071 drivers/gpu/drm/radeon/si.c 	cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
cp_int_cntl      6083 drivers/gpu/drm/radeon/si.c 		cp_int_cntl |= TIME_STAMP_INT_ENABLE;
cp_int_cntl      6103 drivers/gpu/drm/radeon/si.c 	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);