cp_hqd_pq_control 419 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 2 << REG_GET_FIELD(m->cp_hqd_pq_control, cp_hqd_pq_control 320 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 2 << REG_GET_FIELD(m->cp_hqd_pq_control, cp_hqd_pq_control 3339 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_hqd_pq_control = tmp; cp_hqd_pq_control 3450 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mqd->cp_hqd_pq_control); cp_hqd_pq_control 2854 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 cp_hqd_pq_control; cp_hqd_pq_control 2967 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); cp_hqd_pq_control 2968 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control &= cp_hqd_pq_control 2972 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control |= cp_hqd_pq_control 2974 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control |= cp_hqd_pq_control 2977 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control |= cp_hqd_pq_control 2980 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control &= cp_hqd_pq_control 2984 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_control |= cp_hqd_pq_control 4521 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_pq_control = tmp; cp_hqd_pq_control 3500 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_hqd_pq_control = tmp; cp_hqd_pq_control 3610 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mqd->cp_hqd_pq_control); cp_hqd_pq_control 193 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | cp_hqd_pq_control 197 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_control |= PQ_ATC_EN; cp_hqd_pq_control 205 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; cp_hqd_pq_control 215 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_control |= NO_UPDATE_RPTR; cp_hqd_pq_control 319 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | cp_hqd_pq_control 328 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; cp_hqd_pq_control 182 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; cp_hqd_pq_control 183 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_hqd_pq_control |= cp_hqd_pq_control 185 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); cp_hqd_pq_control 223 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | cp_hqd_pq_control 305 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | cp_hqd_pq_control 201 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; cp_hqd_pq_control 202 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; cp_hqd_pq_control 203 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); cp_hqd_pq_control 242 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | cp_hqd_pq_control 323 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | cp_hqd_pq_control 177 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | cp_hqd_pq_control 180 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; cp_hqd_pq_control 181 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); cp_hqd_pq_control 224 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | cp_hqd_pq_control 308 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | cp_hqd_pq_control 96 drivers/gpu/drm/amd/include/cik_structs.h uint32_t cp_hqd_pq_control; cp_hqd_pq_control 822 drivers/gpu/drm/amd/include/v10_structs.h uint32_t cp_hqd_pq_control; cp_hqd_pq_control 305 drivers/gpu/drm/amd/include/v9_structs.h uint32_t cp_hqd_pq_control; cp_hqd_pq_control 305 drivers/gpu/drm/amd/include/vi_structs.h uint32_t cp_hqd_pq_control; cp_hqd_pq_control 4465 drivers/gpu/drm/radeon/cik.c u32 cp_hqd_pq_control; cp_hqd_pq_control 4672 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); cp_hqd_pq_control 4673 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control &= cp_hqd_pq_control 4676 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control |= cp_hqd_pq_control 4678 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control |= cp_hqd_pq_control 4681 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; cp_hqd_pq_control 4683 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control &= cp_hqd_pq_control 4685 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_control |= cp_hqd_pq_control 4687 drivers/gpu/drm/radeon/cik.c WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);