coremask           53 arch/mips/include/asm/mach-netlogic/multi-node.h 	unsigned long	coremask;	/* cores enabled on the soc */
coremask           66 arch/mips/include/asm/mach-netlogic/multi-node.h 					nlm_get_node(n)->coremask != 0)
coremask           12 arch/mips/include/asm/octeon/cvmx-ciu-defs.h #define CVMX_CIU_ADDR(addr, coreid, coremask, offset)			       \
coremask           14 arch/mips/include/asm/octeon/cvmx-ciu-defs.h 	(((coreid) & (coremask)) * offset))
coremask          206 arch/mips/netlogic/common/smp.c 		ncore += hweight32(nlm_get_node(i)->coremask);
coremask           58 arch/mips/netlogic/xlp/nlm_hal.c 		nodep->coremask = 1;	/* node 0, boot cpu */
coremask           55 arch/mips/netlogic/xlp/wakeup.c 	uint32_t coremask, value;
coremask           58 arch/mips/netlogic/xlp/wakeup.c 	coremask = (1 << core);
coremask           63 arch/mips/netlogic/xlp/wakeup.c 		value &= ~coremask;
coremask           70 arch/mips/netlogic/xlp/wakeup.c 		value &= ~coremask;
coremask           77 arch/mips/netlogic/xlp/wakeup.c 	value &= ~coremask;
coremask           88 arch/mips/netlogic/xlp/wakeup.c 	} while ((value & coremask) != 0 && --count > 0);
coremask          191 arch/mips/netlogic/xlp/wakeup.c 			nodep->coremask |= 1u << core;
coremask           86 arch/mips/netlogic/xlr/fmn-config.c 	ncores = hweight32(nlm_current_node()->coremask);
coremask          125 arch/mips/netlogic/xlr/fmn-config.c 	num_core = hweight32(nlm_current_node()->coremask);
coremask          190 arch/mips/netlogic/xlr/fmn-config.c 	num_core = hweight32(nlm_current_node()->coremask);
coremask           71 arch/mips/netlogic/xlr/wakeup.c 	nodep->coremask = 1;
coremask           79 arch/mips/netlogic/xlr/wakeup.c 			nodep->coremask |= (1u << i);
coremask          363 drivers/bcma/host_pci.c 	u32 coremask, tmp;
coremask          379 drivers/bcma/host_pci.c 	coremask = BIT(core->core_index) << 8;
coremask          381 drivers/bcma/host_pci.c 		tmp |= coremask;
coremask          383 drivers/bcma/host_pci.c 		tmp &= ~coremask;
coremask           27 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask,
coremask           36 drivers/crypto/cavium/cpt/cptpf_main.c 		coremask = (coremask << cpt->max_se_cores);
coremask           41 drivers/crypto/cavium/cpt/cptpf_main.c 			(grpmask & ~coremask));
coremask           44 drivers/crypto/cavium/cpt/cptpf_main.c 	while (grp & coremask) {
coremask           45 drivers/crypto/cavium/cpt/cptpf_main.c 		dev_err(dev, "Cores still busy %llx", coremask);
coremask           57 drivers/crypto/cavium/cpt/cptpf_main.c 			(pf_exe_ctl & ~coremask));
coremask           64 drivers/crypto/cavium/cpt/cptpf_main.c static void cpt_enable_cores(struct cpt_device *cpt, u64 coremask,
coremask           70 drivers/crypto/cavium/cpt/cptpf_main.c 		coremask = (coremask << cpt->max_se_cores);
coremask           74 drivers/crypto/cavium/cpt/cptpf_main.c 			(pf_exe_ctl | coremask));
coremask           79 drivers/crypto/cavium/cpt/cptpf_main.c 				u64 coremask, u8 type)
coremask           84 drivers/crypto/cavium/cpt/cptpf_main.c 		coremask = (coremask << cpt->max_se_cores);
coremask           88 drivers/crypto/cavium/cpt/cptpf_main.c 			(pf_gx_en | coremask));
coremask          700 drivers/ssb/driver_pcicore.c 		u32 coremask;
coremask          703 drivers/ssb/driver_pcicore.c 		coremask = (1 << dev->core_index);
coremask          709 drivers/ssb/driver_pcicore.c 		tmp |= coremask << 8;
coremask           88 drivers/staging/netlogic/platform_net.c 	ndata1.cpu_mask = nlm_current_node()->coremask;
coremask          133 drivers/staging/netlogic/platform_net.c 	ndata0.cpu_mask = nlm_current_node()->coremask;
coremask          195 drivers/staging/netlogic/platform_net.c 	ndata0.cpu_mask = nlm_current_node()->coremask;
coremask          174 drivers/usb/musb/musb_dsps.c 	u32 epmask, coremask;
coremask          179 drivers/usb/musb/musb_dsps.c 	coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
coremask          182 drivers/usb/musb/musb_dsps.c 	musb_writel(reg_base, wrp->coreintr_set, coremask);