core_int         3461 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t core_int:1;
core_int         3467 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t core_int:1;
core_int         3487 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t core_int:1;
core_int         3493 arch/mips/include/asm/octeon/cvmx-mio-defs.h 		uint64_t core_int:1;
core_int          251 drivers/crypto/cavium/nitrox/nitrox_hal.c 	union nps_core_int_ena_w1s core_int;
core_int          254 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_int.value = 0;
core_int          255 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_int.s.host_wr_err = 1;
core_int          256 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_int.s.host_wr_timeout = 1;
core_int          257 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_int.s.exec_wr_timeout = 1;
core_int          258 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_int.s.npco_dma_malform = 1;
core_int          259 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_int.s.host_nps_wr_err = 1;
core_int          260 drivers/crypto/cavium/nitrox/nitrox_hal.c 	nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
core_int          178 drivers/crypto/cavium/nitrox/nitrox_isr.c 		union efl_core_int core_int;
core_int          182 drivers/crypto/cavium/nitrox/nitrox_isr.c 		core_int.value = nitrox_read_csr(ndev, offset);
core_int          183 drivers/crypto/cavium/nitrox/nitrox_isr.c 		nitrox_write_csr(ndev, offset, core_int.value);
core_int          185 drivers/crypto/cavium/nitrox/nitrox_isr.c 				    i, core_int.value);
core_int          186 drivers/crypto/cavium/nitrox/nitrox_isr.c 		if (core_int.s.se_err) {
core_int          226 drivers/crypto/cavium/nitrox/nitrox_isr.c 	union nps_core_int_active core_int;
core_int          228 drivers/crypto/cavium/nitrox/nitrox_isr.c 	core_int.value = nitrox_read_csr(ndev, NPS_CORE_INT_ACTIVE);
core_int          230 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.nps_core)
core_int          233 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.nps_pkt)
core_int          236 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.pom)
core_int          239 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.pem)
core_int          242 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.lbc)
core_int          245 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.efl)
core_int          248 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.bmi)
core_int          252 drivers/crypto/cavium/nitrox/nitrox_isr.c 	if (core_int.s.mbox)
core_int          256 drivers/crypto/cavium/nitrox/nitrox_isr.c 	core_int.s.resend = 1;
core_int          257 drivers/crypto/cavium/nitrox/nitrox_isr.c 	nitrox_write_csr(ndev, NPS_CORE_INT_ACTIVE, core_int.value);