core_gbl_vfcfg    265 drivers/crypto/cavium/nitrox/nitrox_hal.c 	union nps_core_gbl_vfcfg core_gbl_vfcfg;
core_gbl_vfcfg    271 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_gbl_vfcfg.value = 0;
core_gbl_vfcfg    272 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_gbl_vfcfg.s.ilk_disable = 1;
core_gbl_vfcfg    273 drivers/crypto/cavium/nitrox/nitrox_hal.c 	core_gbl_vfcfg.s.cfg = __NDEV_MODE_PF;
core_gbl_vfcfg    274 drivers/crypto/cavium/nitrox/nitrox_hal.c 	nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);