core_dc            75 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dc *core_dc = clk_mgr_base->ctx->dc;
core_dc            76 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc           113 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc           129 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dc *core_dc = clk_mgr->base.ctx->dc;
core_dc           130 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc           155 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc            91 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	struct dc *core_dc = clk_mgr->base.ctx->dc;
core_dc            92 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc           103 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc            85 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 	struct dc *core_dc = clk_mgr->base.ctx->dc;
core_dc            86 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc            98 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc           313 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	struct dc  *core_dc = dc;
core_dc           316 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
core_dc           320 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
core_dc           332 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
core_dc          2321 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = link->ctx->dc;
core_dc          2322 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct abm *abm = core_dc->res_pool->abm;
core_dc          2323 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc          2341 drivers/gpu/drm/amd/display/dc/core/dc_link.c 			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
core_dc          2342 drivers/gpu/drm/amd/display/dc/core/dc_link.c 				if (core_dc->current_state->res_ctx.
core_dc          2349 drivers/gpu/drm/amd/display/dc/core/dc_link.c 						core_dc->current_state->
core_dc          2356 drivers/gpu/drm/amd/display/dc/core/dc_link.c 					if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
core_dc          2374 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = link->ctx->dc;
core_dc          2375 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct abm *abm = core_dc->res_pool->abm;
core_dc          2387 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = link->ctx->dc;
core_dc          2388 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc          2676 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
core_dc          2719 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc          2726 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		core_dc->hwss.update_info_frame(pipe_ctx);
core_dc          2763 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		core_dc->hwss.enable_audio_stream(pipe_ctx);
core_dc          2778 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		core_dc->hwss.enable_stream(pipe_ctx);
core_dc          2792 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		core_dc->hwss.unblank_stream(pipe_ctx,
core_dc          2810 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
core_dc          2814 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	core_dc->hwss.blank_stream(pipe_ctx);
core_dc          2843 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	core_dc->hwss.disable_stream(pipe_ctx);
core_dc          2856 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
core_dc          2861 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	core_dc->hwss.set_avmute(pipe_ctx, enable);
core_dc            72 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc  *core_dc = link->ctx->dc;
core_dc            73 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc           177 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc  *core_dc = link->ctx->dc;
core_dc           178 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc           368 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
core_dc           372 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
core_dc           375 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		result = dm_helpers_dp_write_dsc_enable(core_dc->ctx, stream, enable);
core_dc           385 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
core_dc           421 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc           446 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc           489 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
core_dc           508 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc           517 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc          2747 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct dc  *core_dc = dc;
core_dc          2749 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
core_dc           275 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc;
core_dc           293 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	core_dc = stream->ctx->dc;
core_dc           294 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	res_ctx = &core_dc->current_state->res_ctx;
core_dc           306 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			delay_cursor_until_vupdate(pipe_ctx, core_dc);
core_dc           307 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
core_dc           310 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		core_dc->hwss.set_cursor_attribute(pipe_ctx);
core_dc           311 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		if (core_dc->hwss.set_cursor_sdr_white_level)
core_dc           312 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			core_dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
core_dc           316 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
core_dc           326 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc;
core_dc           340 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	core_dc = stream->ctx->dc;
core_dc           341 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	res_ctx = &core_dc->current_state->res_ctx;
core_dc           357 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			delay_cursor_until_vupdate(pipe_ctx, core_dc);
core_dc           358 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 			core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
core_dc           361 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		core_dc->hwss.set_cursor_position(pipe_ctx);
core_dc           365 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
core_dc           488 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc = stream->ctx->dc;
core_dc           490 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		&core_dc->current_state->res_ctx;
core_dc           547 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	struct dc  *core_dc = stream->ctx->dc;
core_dc           549 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 		&core_dc->current_state->res_ctx;
core_dc           115 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	struct dc *core_dc = dc;
core_dc           124 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	construct(core_dc->ctx, plane_state);
core_dc           144 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	struct dc  *core_dc;
core_dc           155 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	core_dc = plane_state->ctx->dc;
core_dc           157 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (core_dc->current_state == NULL)
core_dc           161 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
core_dc           163 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 				&core_dc->current_state->res_ctx.pipe_ctx[i];
core_dc           173 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
core_dc           175 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 				&core_dc->current_state->res_ctx.pipe_ctx[i];
core_dc           180 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		core_dc->hwss.update_pending_status(pipe_ctx);
core_dc           293 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dc *core_dc = clk_mgr->ctx->dc;
core_dc           294 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
core_dc           329 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
core_dc           946 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc *core_dc;
core_dc           954 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	core_dc = pipe_ctx->stream->ctx->dc;
core_dc           955 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	clk_mgr = core_dc->clk_mgr;
core_dc           960 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (core_dc->res_pool->pp_smu)
core_dc           961 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pp_smu = core_dc->res_pool->pp_smu;
core_dc           966 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
core_dc           207 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 	struct dc *core_dc = irq_service->ctx->dc;
core_dc           215 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c 			core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;