cop0 104 arch/mips/include/asm/kvm_host.h #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ cop0 105 arch/mips/include/asm/kvm_host.h ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) cop0 345 arch/mips/include/asm/kvm_host.h struct mips_coproc *cop0; cop0 476 arch/mips/include/asm/kvm_host.h static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \ cop0 478 arch/mips/include/asm/kvm_host.h return cop0->reg[(_reg)][(sel)]; \ cop0 480 arch/mips/include/asm/kvm_host.h static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0, \ cop0 483 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] = val; \ cop0 488 arch/mips/include/asm/kvm_host.h static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \ cop0 491 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val; \ cop0 493 arch/mips/include/asm/kvm_host.h static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \ cop0 496 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~val; \ cop0 498 arch/mips/include/asm/kvm_host.h static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \ cop0 503 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~_mask; \ cop0 504 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val & _mask; \ cop0 509 arch/mips/include/asm/kvm_host.h static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \ cop0 512 arch/mips/include/asm/kvm_host.h _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ cop0 514 arch/mips/include/asm/kvm_host.h static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \ cop0 517 arch/mips/include/asm/kvm_host.h _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ cop0 519 arch/mips/include/asm/kvm_host.h static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \ cop0 523 arch/mips/include/asm/kvm_host.h _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \ cop0 534 arch/mips/include/asm/kvm_host.h static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \ cop0 538 arch/mips/include/asm/kvm_host.h static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0, \ cop0 546 arch/mips/include/asm/kvm_host.h static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0, \ cop0 551 arch/mips/include/asm/kvm_host.h static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0, \ cop0 556 arch/mips/include/asm/kvm_host.h static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0, \ cop0 565 arch/mips/include/asm/kvm_host.h static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0) \ cop0 567 arch/mips/include/asm/kvm_host.h write_gc0_##name(cop0->reg[(_reg)][(sel)]); \ cop0 569 arch/mips/include/asm/kvm_host.h static inline void kvm_save_gc0_##name(struct mips_coproc *cop0) \ cop0 571 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \ cop0 581 arch/mips/include/asm/kvm_host.h static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0) \ cop0 583 arch/mips/include/asm/kvm_host.h return kvm_read_##name2(cop0); \ cop0 585 arch/mips/include/asm/kvm_host.h static inline void kvm_write_##name1(struct mips_coproc *cop0, \ cop0 588 arch/mips/include/asm/kvm_host.h kvm_write_##name2(cop0, val); \ cop0 593 arch/mips/include/asm/kvm_host.h static inline void kvm_set_##name1(struct mips_coproc *cop0, \ cop0 596 arch/mips/include/asm/kvm_host.h kvm_set_##name2(cop0, val); \ cop0 598 arch/mips/include/asm/kvm_host.h static inline void kvm_clear_##name1(struct mips_coproc *cop0, \ cop0 601 arch/mips/include/asm/kvm_host.h kvm_clear_##name2(cop0, val); \ cop0 603 arch/mips/include/asm/kvm_host.h static inline void kvm_change_##name1(struct mips_coproc *cop0, \ cop0 607 arch/mips/include/asm/kvm_host.h kvm_change_##name2(cop0, mask, val); \ cop0 756 arch/mips/include/asm/kvm_host.h kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; cop0 768 arch/mips/include/asm/kvm_host.h kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; cop0 31 arch/mips/kvm/commpage.c vcpu->arch.cop0 = &page->cop0; cop0 17 arch/mips/kvm/commpage.h struct mips_coproc cop0; cop0 114 arch/mips/kvm/dyntrans.c offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); cop0 116 arch/mips/kvm/dyntrans.c if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8) cop0 136 arch/mips/kvm/dyntrans.c offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); cop0 138 arch/mips/kvm/dyntrans.c if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8) cop0 314 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 317 arch/mips/kvm/emulate.c (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC); cop0 386 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 393 arch/mips/kvm/emulate.c compare = kvm_read_c0_guest_compare(cop0); cop0 446 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 450 arch/mips/kvm/emulate.c return kvm_read_c0_guest_count(cop0); cop0 504 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 510 arch/mips/kvm/emulate.c compare = kvm_read_c0_guest_compare(cop0); cop0 605 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 614 arch/mips/kvm/emulate.c kvm_write_c0_guest_count(cop0, count); cop0 651 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 667 arch/mips/kvm/emulate.c count = kvm_read_c0_guest_count(cop0); cop0 698 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 700 arch/mips/kvm/emulate.c u32 old_compare = kvm_read_c0_guest_compare(cop0); cop0 711 arch/mips/kvm/emulate.c kvm_write_c0_guest_compare(cop0, compare); cop0 742 arch/mips/kvm/emulate.c cause = kvm_read_c0_guest_cause(cop0); cop0 744 arch/mips/kvm/emulate.c kvm_write_c0_guest_compare(cop0, compare); cop0 753 arch/mips/kvm/emulate.c kvm_write_c0_guest_cause(cop0, cause); cop0 783 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 793 arch/mips/kvm/emulate.c kvm_write_c0_guest_count(cop0, count); cop0 810 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 812 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_DC); cop0 830 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 833 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_DC); cop0 840 arch/mips/kvm/emulate.c count = kvm_read_c0_guest_count(cop0); cop0 856 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 872 arch/mips/kvm/emulate.c if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) { cop0 884 arch/mips/kvm/emulate.c count = kvm_read_c0_guest_count(cop0); cop0 885 arch/mips/kvm/emulate.c compare = kvm_read_c0_guest_compare(cop0); cop0 948 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 951 arch/mips/kvm/emulate.c if (kvm_read_c0_guest_status(cop0) & ST0_ERL) { cop0 952 arch/mips/kvm/emulate.c kvm_clear_c0_guest_status(cop0, ST0_ERL); cop0 953 arch/mips/kvm/emulate.c vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0); cop0 954 arch/mips/kvm/emulate.c } else if (kvm_read_c0_guest_status(cop0) & ST0_EXL) { cop0 956 arch/mips/kvm/emulate.c kvm_read_c0_guest_epc(cop0)); cop0 957 arch/mips/kvm/emulate.c kvm_clear_c0_guest_status(cop0, ST0_EXL); cop0 958 arch/mips/kvm/emulate.c vcpu->arch.pc = kvm_read_c0_guest_epc(cop0); cop0 997 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1002 arch/mips/kvm/emulate.c if (((kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID) != nasid)) { cop0 1003 arch/mips/kvm/emulate.c trace_kvm_asid_change(vcpu, kvm_read_c0_guest_entryhi(cop0) & cop0 1026 arch/mips/kvm/emulate.c kvm_write_c0_guest_entryhi(cop0, entryhi); cop0 1031 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1036 arch/mips/kvm/emulate.c index = kvm_read_c0_guest_index(cop0); cop0 1044 arch/mips/kvm/emulate.c kvm_write_c0_guest_pagemask(cop0, tlb->tlb_mask); cop0 1045 arch/mips/kvm/emulate.c kvm_write_c0_guest_entrylo0(cop0, tlb->tlb_lo[0]); cop0 1046 arch/mips/kvm/emulate.c kvm_write_c0_guest_entrylo1(cop0, tlb->tlb_lo[1]); cop0 1104 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1105 arch/mips/kvm/emulate.c int index = kvm_read_c0_guest_index(cop0); cop0 1112 arch/mips/kvm/emulate.c pc, index, kvm_read_c0_guest_entryhi(cop0), cop0 1113 arch/mips/kvm/emulate.c kvm_read_c0_guest_entrylo0(cop0), cop0 1114 arch/mips/kvm/emulate.c kvm_read_c0_guest_entrylo1(cop0), cop0 1115 arch/mips/kvm/emulate.c kvm_read_c0_guest_pagemask(cop0)); cop0 1123 arch/mips/kvm/emulate.c tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); cop0 1124 arch/mips/kvm/emulate.c tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); cop0 1125 arch/mips/kvm/emulate.c tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); cop0 1126 arch/mips/kvm/emulate.c tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); cop0 1129 arch/mips/kvm/emulate.c pc, index, kvm_read_c0_guest_entryhi(cop0), cop0 1130 arch/mips/kvm/emulate.c kvm_read_c0_guest_entrylo0(cop0), cop0 1131 arch/mips/kvm/emulate.c kvm_read_c0_guest_entrylo1(cop0), cop0 1132 arch/mips/kvm/emulate.c kvm_read_c0_guest_pagemask(cop0)); cop0 1140 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1150 arch/mips/kvm/emulate.c tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); cop0 1151 arch/mips/kvm/emulate.c tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); cop0 1152 arch/mips/kvm/emulate.c tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); cop0 1153 arch/mips/kvm/emulate.c tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); cop0 1156 arch/mips/kvm/emulate.c pc, index, kvm_read_c0_guest_entryhi(cop0), cop0 1157 arch/mips/kvm/emulate.c kvm_read_c0_guest_entrylo0(cop0), cop0 1158 arch/mips/kvm/emulate.c kvm_read_c0_guest_entrylo1(cop0)); cop0 1165 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1166 arch/mips/kvm/emulate.c long entryhi = kvm_read_c0_guest_entryhi(cop0); cop0 1172 arch/mips/kvm/emulate.c kvm_write_c0_guest_index(cop0, index); cop0 1268 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1317 arch/mips/kvm/emulate.c cop0->stat[rd][sel]++; cop0 1329 arch/mips/kvm/emulate.c vcpu->arch.gprs[rt] = (s32)cop0->reg[rd][sel]; cop0 1342 arch/mips/kvm/emulate.c vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; cop0 1351 arch/mips/kvm/emulate.c cop0->stat[rd][sel]++; cop0 1370 arch/mips/kvm/emulate.c kvm_change_c0_guest_ebase(cop0, 0x1ffff000, cop0 1389 arch/mips/kvm/emulate.c old_val = kvm_read_c0_guest_status(cop0); cop0 1448 arch/mips/kvm/emulate.c kvm_write_c0_guest_status(cop0, val); cop0 1461 arch/mips/kvm/emulate.c old_val = kvm_read_c0_guest_config5(cop0); cop0 1494 arch/mips/kvm/emulate.c kvm_write_c0_guest_config5(cop0, val); cop0 1498 arch/mips/kvm/emulate.c old_cause = kvm_read_c0_guest_cause(cop0); cop0 1501 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, 0x08800300, cop0 1516 arch/mips/kvm/emulate.c if (kvm_read_c0_guest_config3(cop0) & cop0 1519 arch/mips/kvm/emulate.c cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask; cop0 1521 arch/mips/kvm/emulate.c cop0->reg[rd][sel] = vcpu->arch.gprs[rt]; cop0 1539 arch/mips/kvm/emulate.c cop0->stat[MIPS_CP0_STATUS][0]++; cop0 1543 arch/mips/kvm/emulate.c kvm_read_c0_guest_status(cop0); cop0 1548 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_IE); cop0 1552 arch/mips/kvm/emulate.c kvm_clear_c0_guest_status(cop0, ST0_IE); cop0 1559 arch/mips/kvm/emulate.c u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf; cop0 1561 arch/mips/kvm/emulate.c (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf; cop0 1993 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1995 arch/mips/kvm/emulate.c if (kvm_read_c0_guest_status(cop0) & ST0_BEV) cop0 1998 arch/mips/kvm/emulate.c return kvm_read_c0_guest_ebase(cop0) & MIPS_EBASE_BASE; cop0 2006 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2010 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2012 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2013 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2016 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2018 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2022 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2041 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2044 arch/mips/kvm/emulate.c (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); cop0 2046 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2048 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2049 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2052 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2054 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2069 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2073 arch/mips/kvm/emulate.c kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); cop0 2075 arch/mips/kvm/emulate.c kvm_write_c0_guest_entryhi(cop0, entryhi); cop0 2085 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2089 arch/mips/kvm/emulate.c (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); cop0 2091 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2093 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2094 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2097 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2099 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2111 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2115 arch/mips/kvm/emulate.c kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); cop0 2117 arch/mips/kvm/emulate.c kvm_write_c0_guest_entryhi(cop0, entryhi); cop0 2127 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2130 arch/mips/kvm/emulate.c (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); cop0 2132 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2134 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2135 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2138 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2140 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2153 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2157 arch/mips/kvm/emulate.c kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); cop0 2159 arch/mips/kvm/emulate.c kvm_write_c0_guest_entryhi(cop0, entryhi); cop0 2169 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2172 arch/mips/kvm/emulate.c (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); cop0 2174 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2176 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2177 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2180 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2182 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2194 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2198 arch/mips/kvm/emulate.c kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); cop0 2200 arch/mips/kvm/emulate.c kvm_write_c0_guest_entryhi(cop0, entryhi); cop0 2210 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2212 arch/mips/kvm/emulate.c (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); cop0 2215 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2217 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2218 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2221 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2223 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2234 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2238 arch/mips/kvm/emulate.c kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); cop0 2240 arch/mips/kvm/emulate.c kvm_write_c0_guest_entryhi(cop0, entryhi); cop0 2250 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2253 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2255 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2256 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2259 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2261 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2267 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2269 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE)); cop0 2279 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2283 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2285 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2286 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2289 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2291 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2295 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2314 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2318 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2320 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2321 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2324 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2326 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2330 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2349 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2353 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2355 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2356 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2359 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2361 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2365 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2384 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2388 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2390 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2391 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2394 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2396 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2400 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2419 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2423 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2425 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2426 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2429 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2431 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2435 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2454 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2458 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2460 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2461 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2464 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2466 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2470 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2488 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2523 arch/mips/kvm/emulate.c if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) { cop0 2550 arch/mips/kvm/emulate.c arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0); cop0 2629 arch/mips/kvm/emulate.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2633 arch/mips/kvm/emulate.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 2635 arch/mips/kvm/emulate.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 2636 arch/mips/kvm/emulate.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 2639 arch/mips/kvm/emulate.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 2641 arch/mips/kvm/emulate.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 2643 arch/mips/kvm/emulate.c kvm_change_c0_guest_cause(cop0, (0xff), cop0 2648 arch/mips/kvm/emulate.c kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); cop0 2651 arch/mips/kvm/emulate.c exccode, kvm_read_c0_guest_epc(cop0), cop0 2652 arch/mips/kvm/emulate.c kvm_read_c0_guest_badvaddr(cop0)); cop0 2779 arch/mips/kvm/emulate.c (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) & cop0 369 arch/mips/kvm/entry.c UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, cop0), K1); cop0 41 arch/mips/kvm/interrupt.c kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI)); cop0 50 arch/mips/kvm/interrupt.c kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI)); cop0 66 arch/mips/kvm/interrupt.c kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0)); cop0 72 arch/mips/kvm/interrupt.c kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1)); cop0 77 arch/mips/kvm/interrupt.c kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2)); cop0 94 arch/mips/kvm/interrupt.c kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0)); cop0 99 arch/mips/kvm/interrupt.c kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1)); cop0 104 arch/mips/kvm/interrupt.c kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2)); cop0 122 arch/mips/kvm/interrupt.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 126 arch/mips/kvm/interrupt.c if ((kvm_read_c0_guest_status(cop0) & ST0_IE) cop0 127 arch/mips/kvm/interrupt.c && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL))) cop0 128 arch/mips/kvm/interrupt.c && (kvm_read_c0_guest_status(cop0) & IE_IRQ5)) { cop0 135 arch/mips/kvm/interrupt.c if ((kvm_read_c0_guest_status(cop0) & ST0_IE) cop0 136 arch/mips/kvm/interrupt.c && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL))) cop0 137 arch/mips/kvm/interrupt.c && (kvm_read_c0_guest_status(cop0) & IE_IRQ0)) { cop0 144 arch/mips/kvm/interrupt.c if ((kvm_read_c0_guest_status(cop0) & ST0_IE) cop0 145 arch/mips/kvm/interrupt.c && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL))) cop0 146 arch/mips/kvm/interrupt.c && (kvm_read_c0_guest_status(cop0) & IE_IRQ1)) { cop0 153 arch/mips/kvm/interrupt.c if ((kvm_read_c0_guest_status(cop0) & ST0_IE) cop0 154 arch/mips/kvm/interrupt.c && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL))) cop0 155 arch/mips/kvm/interrupt.c && (kvm_read_c0_guest_status(cop0) & IE_IRQ2)) { cop0 167 arch/mips/kvm/interrupt.c if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { cop0 169 arch/mips/kvm/interrupt.c kvm_write_c0_guest_epc(cop0, arch->pc); cop0 170 arch/mips/kvm/interrupt.c kvm_set_c0_guest_status(cop0, ST0_EXL); cop0 173 arch/mips/kvm/interrupt.c kvm_set_c0_guest_cause(cop0, CAUSEF_BD); cop0 175 arch/mips/kvm/interrupt.c kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); cop0 182 arch/mips/kvm/interrupt.c kvm_change_c0_guest_cause(cop0, CAUSEF_EXCCODE, cop0 187 arch/mips/kvm/interrupt.c if (kvm_read_c0_guest_cause(cop0) & CAUSEF_IV) cop0 647 arch/mips/kvm/mips.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 677 arch/mips/kvm/mips.c if (kvm_read_c0_guest_status(cop0) & ST0_FR) cop0 687 arch/mips/kvm/mips.c if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) cop0 707 arch/mips/kvm/mips.c if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) cop0 759 arch/mips/kvm/mips.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 811 arch/mips/kvm/mips.c if (kvm_read_c0_guest_status(cop0) & ST0_FR) cop0 821 arch/mips/kvm/mips.c if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) cop0 1147 arch/mips/kvm/mips.c kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI; cop0 1153 arch/mips/kvm/mips.c struct mips_coproc *cop0; cop0 1171 arch/mips/kvm/mips.c cop0 = vcpu->arch.cop0; cop0 1173 arch/mips/kvm/mips.c kvm_read_c0_guest_status(cop0), cop0 1174 arch/mips/kvm/mips.c kvm_read_c0_guest_cause(cop0)); cop0 1176 arch/mips/kvm/mips.c kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); cop0 1358 arch/mips/kvm/mips.c cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, cop0 1430 arch/mips/kvm/mips.c kvm_read_c0_guest_status(vcpu->arch.cop0)); cop0 1498 arch/mips/kvm/mips.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1503 arch/mips/kvm/mips.c sr = kvm_read_c0_guest_status(cop0); cop0 1525 arch/mips/kvm/mips.c cfg5 = kvm_read_c0_guest_config5(cop0); cop0 1546 arch/mips/kvm/mips.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1556 arch/mips/kvm/mips.c sr = kvm_read_c0_guest_status(cop0); cop0 1569 arch/mips/kvm/mips.c cfg5 = kvm_read_c0_guest_config5(cop0); cop0 1200 arch/mips/kvm/mmu.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1211 arch/mips/kvm/mmu.c (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID)); cop0 57 arch/mips/kvm/stats.c if (vcpu->arch.cop0->stat[i][j]) cop0 59 arch/mips/kvm/stats.c vcpu->arch.cop0->stat[i][j]); cop0 90 arch/mips/kvm/tlb.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 95 arch/mips/kvm/tlb.c kvm_info("Guest EntryHi: %#lx\n", kvm_read_c0_guest_entryhi(cop0)); cop0 325 arch/mips/kvm/trace.h __entry->epc = kvm_read_c0_guest_epc(vcpu->arch.cop0); cop0 327 arch/mips/kvm/trace.h __entry->badvaddr = kvm_read_c0_guest_badvaddr(vcpu->arch.cop0); cop0 328 arch/mips/kvm/trace.h __entry->status = kvm_read_c0_guest_status(vcpu->arch.cop0); cop0 329 arch/mips/kvm/trace.h __entry->cause = kvm_read_c0_guest_cause(vcpu->arch.cop0); cop0 61 arch/mips/kvm/trap_emul.c kvm_read_c0_guest_status(vcpu->arch.cop0)); cop0 69 arch/mips/kvm/trap_emul.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 79 arch/mips/kvm/trap_emul.c (kvm_read_c0_guest_status(cop0) & ST0_CU1) == 0) { cop0 190 arch/mips/kvm/trap_emul.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 207 arch/mips/kvm/trap_emul.c (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); cop0 476 arch/mips/kvm/trap_emul.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 484 arch/mips/kvm/trap_emul.c (kvm_read_c0_guest_status(cop0) & (ST0_CU1 | ST0_FR)) == ST0_CU1) { cop0 490 arch/mips/kvm/trap_emul.c } else if (!(kvm_read_c0_guest_config5(cop0) & MIPS_CONF5_MSAEN)) { cop0 613 arch/mips/kvm/trap_emul.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 626 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_prid(cop0, 0x00019300); cop0 629 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_prid(cop0, 0x00010000); cop0 643 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config(cop0, config); cop0 662 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config1(cop0, config1); cop0 665 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config2(cop0, MIPS_CONF_M); cop0 669 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config3(cop0, MIPS_CONF_M | MIPS_CONF3_ULRI); cop0 672 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config4(cop0, MIPS_CONF_M); cop0 675 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config5(cop0, 0); cop0 678 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10)); cop0 681 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_status(cop0, ST0_BEV | ST0_ERL); cop0 686 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_intctl(cop0, 0xFC000000); cop0 689 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 | cop0 769 arch/mips/kvm/trap_emul.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 773 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_index(cop0); cop0 776 arch/mips/kvm/trap_emul.c *v = kvm_read_c0_guest_entrylo0(cop0); cop0 779 arch/mips/kvm/trap_emul.c *v = kvm_read_c0_guest_entrylo1(cop0); cop0 782 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_context(cop0); cop0 785 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_userlocal(cop0); cop0 788 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_pagemask(cop0); cop0 791 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_wired(cop0); cop0 794 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_hwrena(cop0); cop0 797 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_badvaddr(cop0); cop0 800 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_entryhi(cop0); cop0 803 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_compare(cop0); cop0 806 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_status(cop0); cop0 809 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_intctl(cop0); cop0 812 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_cause(cop0); cop0 815 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_epc(cop0); cop0 818 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_prid(cop0); cop0 821 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_ebase(cop0); cop0 824 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_config(cop0); cop0 827 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_config1(cop0); cop0 830 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_config2(cop0); cop0 833 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_config3(cop0); cop0 836 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_config4(cop0); cop0 839 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_config5(cop0); cop0 842 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_config7(cop0); cop0 857 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_errorepc(cop0); cop0 860 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_kscratch1(cop0); cop0 863 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_kscratch2(cop0); cop0 866 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_kscratch3(cop0); cop0 869 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_kscratch4(cop0); cop0 872 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_kscratch5(cop0); cop0 875 arch/mips/kvm/trap_emul.c *v = (long)kvm_read_c0_guest_kscratch6(cop0); cop0 887 arch/mips/kvm/trap_emul.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 893 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_index(cop0, v); cop0 896 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_entrylo0(cop0, v); cop0 899 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_entrylo1(cop0, v); cop0 902 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_context(cop0, v); cop0 905 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_userlocal(cop0, v); cop0 908 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_pagemask(cop0, v); cop0 911 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_wired(cop0, v); cop0 914 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_hwrena(cop0, v); cop0 917 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_badvaddr(cop0, v); cop0 920 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_entryhi(cop0, v); cop0 923 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_status(cop0, v); cop0 929 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_epc(cop0, v); cop0 932 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_prid(cop0, v); cop0 939 arch/mips/kvm/trap_emul.c kvm_change_c0_guest_ebase(cop0, 0x1ffff000 | MIPS_EBASE_CPUNUM, cop0 954 arch/mips/kvm/trap_emul.c if ((kvm_read_c0_guest_cause(cop0) ^ v) & CAUSEF_DC) { cop0 958 arch/mips/kvm/trap_emul.c kvm_change_c0_guest_cause(cop0, (u32)~CAUSEF_DC, cop0 962 arch/mips/kvm/trap_emul.c kvm_change_c0_guest_cause(cop0, (u32)~CAUSEF_DC, cop0 967 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_cause(cop0, v); cop0 974 arch/mips/kvm/trap_emul.c cur = kvm_read_c0_guest_config1(cop0); cop0 978 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config1(cop0, v); cop0 985 arch/mips/kvm/trap_emul.c cur = kvm_read_c0_guest_config3(cop0); cop0 989 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config3(cop0, v); cop0 993 arch/mips/kvm/trap_emul.c cur = kvm_read_c0_guest_config4(cop0); cop0 997 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config4(cop0, v); cop0 1001 arch/mips/kvm/trap_emul.c cur = kvm_read_c0_guest_config5(cop0); cop0 1005 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_config5(cop0, v); cop0 1021 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_errorepc(cop0, v); cop0 1024 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_kscratch1(cop0, v); cop0 1027 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_kscratch2(cop0, v); cop0 1030 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_kscratch3(cop0, v); cop0 1033 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_kscratch4(cop0, v); cop0 1036 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_kscratch5(cop0, v); cop0 1039 arch/mips/kvm/trap_emul.c kvm_write_c0_guest_kscratch6(cop0, v); cop0 1188 arch/mips/kvm/trap_emul.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1210 arch/mips/kvm/trap_emul.c gasid = kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID; cop0 1233 arch/mips/kvm/trap_emul.c kvm_read_c0_guest_cause(vcpu->arch.cop0)); cop0 450 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 453 arch/mips/kvm/vz.c compare = kvm_read_sw_gc0_compare(cop0); cop0 454 arch/mips/kvm/vz.c cause = kvm_read_sw_gc0_cause(cop0); cop0 545 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 561 arch/mips/kvm/vz.c kvm_write_sw_gc0_cause(cop0, cause); cop0 562 arch/mips/kvm/vz.c kvm_write_sw_gc0_compare(cop0, compare); cop0 891 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 895 arch/mips/kvm/vz.c kvm_write_sw_gc0_maari(cop0, ARRAY_SIZE(vcpu->arch.maar) - 1); cop0 897 arch/mips/kvm/vz.c kvm_write_sw_gc0_maari(cop0, val); cop0 905 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 937 arch/mips/kvm/vz.c cop0->stat[rd][sel]++; cop0 957 arch/mips/kvm/vz.c BUG_ON(kvm_read_sw_gc0_maari(cop0) >= cop0 960 arch/mips/kvm/vz.c kvm_read_sw_gc0_maari(cop0)]; cop0 976 arch/mips/kvm/vz.c val = cop0->reg[rd][sel]; cop0 997 arch/mips/kvm/vz.c cop0->stat[rd][sel]++; cop0 1030 arch/mips/kvm/vz.c BUG_ON(kvm_read_sw_gc0_maari(cop0) >= cop0 1032 arch/mips/kvm/vz.c vcpu->arch.maar[kvm_read_sw_gc0_maari(cop0)] = cop0 1826 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 1947 arch/mips/kvm/vz.c *v = (long)kvm_read_c0_guest_prid(cop0); cop0 1993 arch/mips/kvm/vz.c *v = kvm_read_sw_gc0_maari(vcpu->arch.cop0); cop0 2047 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2186 arch/mips/kvm/vz.c kvm_write_c0_guest_prid(cop0, v); cop0 2466 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2486 arch/mips/kvm/vz.c kvm_restore_gc0_wired(cop0); cop0 2514 arch/mips/kvm/vz.c kvm_restore_gc0_config(cop0); cop0 2516 arch/mips/kvm/vz.c kvm_restore_gc0_config1(cop0); cop0 2518 arch/mips/kvm/vz.c kvm_restore_gc0_config2(cop0); cop0 2520 arch/mips/kvm/vz.c kvm_restore_gc0_config3(cop0); cop0 2522 arch/mips/kvm/vz.c kvm_restore_gc0_config4(cop0); cop0 2524 arch/mips/kvm/vz.c kvm_restore_gc0_config5(cop0); cop0 2526 arch/mips/kvm/vz.c kvm_restore_gc0_config6(cop0); cop0 2528 arch/mips/kvm/vz.c kvm_restore_gc0_config7(cop0); cop0 2530 arch/mips/kvm/vz.c kvm_restore_gc0_index(cop0); cop0 2531 arch/mips/kvm/vz.c kvm_restore_gc0_entrylo0(cop0); cop0 2532 arch/mips/kvm/vz.c kvm_restore_gc0_entrylo1(cop0); cop0 2533 arch/mips/kvm/vz.c kvm_restore_gc0_context(cop0); cop0 2535 arch/mips/kvm/vz.c kvm_restore_gc0_contextconfig(cop0); cop0 2537 arch/mips/kvm/vz.c kvm_restore_gc0_xcontext(cop0); cop0 2539 arch/mips/kvm/vz.c kvm_restore_gc0_xcontextconfig(cop0); cop0 2541 arch/mips/kvm/vz.c kvm_restore_gc0_pagemask(cop0); cop0 2542 arch/mips/kvm/vz.c kvm_restore_gc0_pagegrain(cop0); cop0 2543 arch/mips/kvm/vz.c kvm_restore_gc0_hwrena(cop0); cop0 2544 arch/mips/kvm/vz.c kvm_restore_gc0_badvaddr(cop0); cop0 2545 arch/mips/kvm/vz.c kvm_restore_gc0_entryhi(cop0); cop0 2546 arch/mips/kvm/vz.c kvm_restore_gc0_status(cop0); cop0 2547 arch/mips/kvm/vz.c kvm_restore_gc0_intctl(cop0); cop0 2548 arch/mips/kvm/vz.c kvm_restore_gc0_epc(cop0); cop0 2549 arch/mips/kvm/vz.c kvm_vz_write_gc0_ebase(kvm_read_sw_gc0_ebase(cop0)); cop0 2551 arch/mips/kvm/vz.c kvm_restore_gc0_userlocal(cop0); cop0 2553 arch/mips/kvm/vz.c kvm_restore_gc0_errorepc(cop0); cop0 2558 arch/mips/kvm/vz.c kvm_restore_gc0_kscratch1(cop0); cop0 2560 arch/mips/kvm/vz.c kvm_restore_gc0_kscratch2(cop0); cop0 2562 arch/mips/kvm/vz.c kvm_restore_gc0_kscratch3(cop0); cop0 2564 arch/mips/kvm/vz.c kvm_restore_gc0_kscratch4(cop0); cop0 2566 arch/mips/kvm/vz.c kvm_restore_gc0_kscratch5(cop0); cop0 2568 arch/mips/kvm/vz.c kvm_restore_gc0_kscratch6(cop0); cop0 2572 arch/mips/kvm/vz.c kvm_restore_gc0_badinstr(cop0); cop0 2574 arch/mips/kvm/vz.c kvm_restore_gc0_badinstrp(cop0); cop0 2577 arch/mips/kvm/vz.c kvm_restore_gc0_segctl0(cop0); cop0 2578 arch/mips/kvm/vz.c kvm_restore_gc0_segctl1(cop0); cop0 2579 arch/mips/kvm/vz.c kvm_restore_gc0_segctl2(cop0); cop0 2584 arch/mips/kvm/vz.c kvm_restore_gc0_pwbase(cop0); cop0 2585 arch/mips/kvm/vz.c kvm_restore_gc0_pwfield(cop0); cop0 2586 arch/mips/kvm/vz.c kvm_restore_gc0_pwsize(cop0); cop0 2587 arch/mips/kvm/vz.c kvm_restore_gc0_pwctl(cop0); cop0 2593 arch/mips/kvm/vz.c cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL]); cop0 2608 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2615 arch/mips/kvm/vz.c kvm_save_gc0_index(cop0); cop0 2616 arch/mips/kvm/vz.c kvm_save_gc0_entrylo0(cop0); cop0 2617 arch/mips/kvm/vz.c kvm_save_gc0_entrylo1(cop0); cop0 2618 arch/mips/kvm/vz.c kvm_save_gc0_context(cop0); cop0 2620 arch/mips/kvm/vz.c kvm_save_gc0_contextconfig(cop0); cop0 2622 arch/mips/kvm/vz.c kvm_save_gc0_xcontext(cop0); cop0 2624 arch/mips/kvm/vz.c kvm_save_gc0_xcontextconfig(cop0); cop0 2626 arch/mips/kvm/vz.c kvm_save_gc0_pagemask(cop0); cop0 2627 arch/mips/kvm/vz.c kvm_save_gc0_pagegrain(cop0); cop0 2628 arch/mips/kvm/vz.c kvm_save_gc0_wired(cop0); cop0 2631 arch/mips/kvm/vz.c kvm_save_gc0_hwrena(cop0); cop0 2632 arch/mips/kvm/vz.c kvm_save_gc0_badvaddr(cop0); cop0 2633 arch/mips/kvm/vz.c kvm_save_gc0_entryhi(cop0); cop0 2634 arch/mips/kvm/vz.c kvm_save_gc0_status(cop0); cop0 2635 arch/mips/kvm/vz.c kvm_save_gc0_intctl(cop0); cop0 2636 arch/mips/kvm/vz.c kvm_save_gc0_epc(cop0); cop0 2637 arch/mips/kvm/vz.c kvm_write_sw_gc0_ebase(cop0, kvm_vz_read_gc0_ebase()); cop0 2639 arch/mips/kvm/vz.c kvm_save_gc0_userlocal(cop0); cop0 2642 arch/mips/kvm/vz.c kvm_save_gc0_config(cop0); cop0 2644 arch/mips/kvm/vz.c kvm_save_gc0_config1(cop0); cop0 2646 arch/mips/kvm/vz.c kvm_save_gc0_config2(cop0); cop0 2648 arch/mips/kvm/vz.c kvm_save_gc0_config3(cop0); cop0 2650 arch/mips/kvm/vz.c kvm_save_gc0_config4(cop0); cop0 2652 arch/mips/kvm/vz.c kvm_save_gc0_config5(cop0); cop0 2654 arch/mips/kvm/vz.c kvm_save_gc0_config6(cop0); cop0 2656 arch/mips/kvm/vz.c kvm_save_gc0_config7(cop0); cop0 2658 arch/mips/kvm/vz.c kvm_save_gc0_errorepc(cop0); cop0 2663 arch/mips/kvm/vz.c kvm_save_gc0_kscratch1(cop0); cop0 2665 arch/mips/kvm/vz.c kvm_save_gc0_kscratch2(cop0); cop0 2667 arch/mips/kvm/vz.c kvm_save_gc0_kscratch3(cop0); cop0 2669 arch/mips/kvm/vz.c kvm_save_gc0_kscratch4(cop0); cop0 2671 arch/mips/kvm/vz.c kvm_save_gc0_kscratch5(cop0); cop0 2673 arch/mips/kvm/vz.c kvm_save_gc0_kscratch6(cop0); cop0 2677 arch/mips/kvm/vz.c kvm_save_gc0_badinstr(cop0); cop0 2679 arch/mips/kvm/vz.c kvm_save_gc0_badinstrp(cop0); cop0 2682 arch/mips/kvm/vz.c kvm_save_gc0_segctl0(cop0); cop0 2683 arch/mips/kvm/vz.c kvm_save_gc0_segctl1(cop0); cop0 2684 arch/mips/kvm/vz.c kvm_save_gc0_segctl2(cop0); cop0 2689 arch/mips/kvm/vz.c kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) { cop0 2690 arch/mips/kvm/vz.c kvm_save_gc0_pwbase(cop0); cop0 2691 arch/mips/kvm/vz.c kvm_save_gc0_pwfield(cop0); cop0 2692 arch/mips/kvm/vz.c kvm_save_gc0_pwsize(cop0); cop0 2693 arch/mips/kvm/vz.c kvm_save_gc0_pwctl(cop0); cop0 2700 arch/mips/kvm/vz.c cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = cop0 2967 arch/mips/kvm/vz.c struct mips_coproc *cop0 = vcpu->arch.cop0; cop0 2984 arch/mips/kvm/vz.c kvm_write_sw_gc0_pagegrain(cop0, PG_RIE | PG_XIE | PG_IEC); cop0 2987 arch/mips/kvm/vz.c kvm_write_sw_gc0_wired(cop0, cop0 2990 arch/mips/kvm/vz.c kvm_write_sw_gc0_status(cop0, ST0_BEV | ST0_ERL); cop0 2992 arch/mips/kvm/vz.c kvm_change_sw_gc0_status(cop0, ST0_FR, read_gc0_status()); cop0 2994 arch/mips/kvm/vz.c kvm_write_sw_gc0_intctl(cop0, read_gc0_intctl() & cop0 2997 arch/mips/kvm/vz.c kvm_write_sw_gc0_prid(cop0, boot_cpu_data.processor_id); cop0 2999 arch/mips/kvm/vz.c kvm_write_sw_gc0_ebase(cop0, (s32)0x80000000 | vcpu->vcpu_id); cop0 3001 arch/mips/kvm/vz.c kvm_save_gc0_config(cop0); cop0 3003 arch/mips/kvm/vz.c kvm_change_sw_gc0_config(cop0, CONF_CM_CMASK, cop0 3006 arch/mips/kvm/vz.c kvm_change_sw_gc0_config(cop0, MIPS_CONF_MT, read_c0_config()); cop0 3008 arch/mips/kvm/vz.c kvm_set_sw_gc0_config(cop0, MIPS_CONF_M); cop0 3010 arch/mips/kvm/vz.c kvm_save_gc0_config1(cop0); cop0 3012 arch/mips/kvm/vz.c kvm_clear_sw_gc0_config1(cop0, MIPS_CONF1_C2 | cop0 3020 arch/mips/kvm/vz.c kvm_set_sw_gc0_config1(cop0, MIPS_CONF_M); cop0 3022 arch/mips/kvm/vz.c kvm_save_gc0_config2(cop0); cop0 3025 arch/mips/kvm/vz.c kvm_set_sw_gc0_config2(cop0, MIPS_CONF_M); cop0 3027 arch/mips/kvm/vz.c kvm_save_gc0_config3(cop0); cop0 3029 arch/mips/kvm/vz.c kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_ISA_OE); cop0 3031 arch/mips/kvm/vz.c kvm_clear_sw_gc0_config3(cop0, MIPS_CONF3_MSA | cop0 3047 arch/mips/kvm/vz.c kvm_set_sw_gc0_config3(cop0, MIPS_CONF_M); cop0 3049 arch/mips/kvm/vz.c kvm_save_gc0_config4(cop0); cop0 3052 arch/mips/kvm/vz.c kvm_set_sw_gc0_config4(cop0, MIPS_CONF_M); cop0 3054 arch/mips/kvm/vz.c kvm_save_gc0_config5(cop0); cop0 3056 arch/mips/kvm/vz.c kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_K | cop0 3064 arch/mips/kvm/vz.c kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP); cop0 3069 arch/mips/kvm/vz.c kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0); cop0 3073 arch/mips/kvm/vz.c kvm_write_sw_gc0_xcontextconfig(cop0, cop0 3081 arch/mips/kvm/vz.c kvm_write_sw_gc0_segctl0(cop0, 0x00200010); cop0 3082 arch/mips/kvm/vz.c kvm_write_sw_gc0_segctl1(cop0, 0x00000002 | cop0 3085 arch/mips/kvm/vz.c kvm_write_sw_gc0_segctl2(cop0, 0x00380438); cop0 3091 arch/mips/kvm/vz.c kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302); cop0 3093 arch/mips/kvm/vz.c kvm_write_sw_gc0_pwsize(cop0, 1 << MIPS_PWSIZE_PTW_SHIFT); cop0 3098 arch/mips/kvm/vz.c cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0;