control_value      81 arch/arm/mach-ixp4xx/goramo_mlr.c static u8 control_value;
control_value     110 arch/arm/mach-ixp4xx/goramo_mlr.c 		control_value |=  (1 << line);
control_value     112 arch/arm/mach-ixp4xx/goramo_mlr.c 		control_value &= ~(1 << line);
control_value     125 arch/arm/mach-ixp4xx/goramo_mlr.c 		set_sda(control_value & (0x80 >> i)); /* MSB first */
control_value     133 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	unsigned int control_value = 0;
control_value     143 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
control_value     144 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
control_value     146 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
control_value     147 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
control_value     148 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
control_value      32 drivers/gpu/drm/i915/gt/intel_mocs.c 	u32 control_value;
control_value      88 drivers/gpu/drm/i915/gt/intel_mocs.c 		.control_value = __control_value, \
control_value     355 drivers/gpu/drm/i915/gt/intel_mocs.c 		return table->table[index].control_value;
control_value     357 drivers/gpu/drm/i915/gt/intel_mocs.c 	return table->table[I915_MOCS_PTE].control_value;
control_value     386 drivers/gpu/drm/i915/gt/intel_mocs.c 	unused_value = table.table[I915_MOCS_PTE].control_value;
control_value     420 drivers/gpu/drm/i915/gt/intel_mocs.c 				   table.table[index].control_value);
control_value     430 drivers/gpu/drm/i915/gt/intel_mocs.c 				   table.table[0].control_value);
control_value     445 drivers/gpu/drm/i915/gt/intel_mocs.c 	unused_value = table->table[I915_MOCS_PTE].control_value;
control_value     110 drivers/mmc/host/sdhci-pci-gli.c 	u32 control_value;
control_value     120 drivers/mmc/host/sdhci-pci-gli.c 	control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
control_value     159 drivers/mmc/host/sdhci-pci-gli.c 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
control_value     160 drivers/mmc/host/sdhci-pci-gli.c 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
control_value     161 drivers/mmc/host/sdhci-pci-gli.c 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
control_value     163 drivers/mmc/host/sdhci-pci-gli.c 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
control_value     175 drivers/mmc/host/sdhci-pci-gli.c 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
control_value     176 drivers/mmc/host/sdhci-pci-gli.c 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
control_value     178 drivers/mmc/host/sdhci-pci-gli.c 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
control_value     184 drivers/mmc/host/sdhci-pci-gli.c 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
control_value     185 drivers/mmc/host/sdhci-pci-gli.c 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
control_value     187 drivers/mmc/host/sdhci-pci-gli.c 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
control_value    1424 drivers/net/ethernet/qlogic/netxen/netxen_nic.h 		u32 control_value;
control_value    1499 drivers/net/ethernet/qlogic/netxen/netxen_nic.h 		u32 control_value;