control_reg 139 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c union cvmx_pcsx_mrx_control_reg control_reg; control_reg 149 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c control_reg.u64 = control_reg 152 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c control_reg.s.reset = 1; control_reg 154 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c control_reg.u64); control_reg 169 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c control_reg.s.rst_an = 1; control_reg 170 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c control_reg.s.an_en = 1; control_reg 171 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c control_reg.s.pwr_dn = 0; control_reg 173 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c control_reg.u64); control_reg 35 drivers/clk/clk-palmas.c unsigned int control_reg; control_reg 67 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, control_reg 72 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); control_reg 92 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, control_reg 96 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); control_reg 109 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, &val); control_reg 112 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); control_reg 138 drivers/clk/clk-palmas.c .control_reg = PALMAS_CLK32KG_CTRL, control_reg 154 drivers/clk/clk-palmas.c .control_reg = PALMAS_CLK32KGAUDIO_CTRL, control_reg 211 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, control_reg 215 drivers/clk/clk-palmas.c cinfo->clk_desc->control_reg, ret); control_reg 63 drivers/clk/ti/apll.c v = ti_clk_ll_ops->clk_readl(&ad->control_reg); control_reg 66 drivers/clk/ti/apll.c ti_clk_ll_ops->clk_writel(v, &ad->control_reg); control_reg 102 drivers/clk/ti/apll.c v = ti_clk_ll_ops->clk_readl(&ad->control_reg); control_reg 105 drivers/clk/ti/apll.c ti_clk_ll_ops->clk_writel(v, &ad->control_reg); control_reg 116 drivers/clk/ti/apll.c v = ti_clk_ll_ops->clk_readl(&ad->control_reg); control_reg 218 drivers/clk/ti/apll.c ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); control_reg 247 drivers/clk/ti/apll.c v = ti_clk_ll_ops->clk_readl(&ad->control_reg); control_reg 273 drivers/clk/ti/apll.c v = ti_clk_ll_ops->clk_readl(&ad->control_reg); control_reg 276 drivers/clk/ti/apll.c ti_clk_ll_ops->clk_writel(v, &ad->control_reg); control_reg 303 drivers/clk/ti/apll.c v = ti_clk_ll_ops->clk_readl(&ad->control_reg); control_reg 306 drivers/clk/ti/apll.c ti_clk_ll_ops->clk_writel(v, &ad->control_reg); control_reg 324 drivers/clk/ti/apll.c ti_clk_ll_ops->clk_writel(v, &ad->control_reg); control_reg 399 drivers/clk/ti/apll.c ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); control_reg 213 drivers/clk/ti/clkt_dpll.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 249 drivers/clk/ti/clkt_dpll.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 322 drivers/clk/ti/dpll.c if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) control_reg 54 drivers/clk/ti/dpll3xxx.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 57 drivers/clk/ti/dpll3xxx.c ti_clk_ll_ops->clk_writel(v, &dd->control_reg); control_reg 317 drivers/clk/ti/dpll3xxx.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 320 drivers/clk/ti/dpll3xxx.c ti_clk_ll_ops->clk_writel(v, &dd->control_reg); control_reg 374 drivers/clk/ti/dpll3xxx.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 390 drivers/clk/ti/dpll3xxx.c ti_clk_ll_ops->clk_writel(v, &dd->control_reg); control_reg 773 drivers/clk/ti/dpll3xxx.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask; control_reg 797 drivers/clk/ti/dpll3xxx.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 858 drivers/clk/ti/dpll3xxx.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 887 drivers/clk/ti/dpll3xxx.c ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 128 drivers/clk/ti/dpll44xx.c v = ti_clk_ll_ops->clk_readl(&dd->control_reg); control_reg 390 drivers/i2c/busses/i2c-mt65xx.c u16 control_reg; control_reg 415 drivers/i2c/busses/i2c-mt65xx.c control_reg = I2C_CONTROL_ACKERR_DET_EN | control_reg 418 drivers/i2c/busses/i2c-mt65xx.c control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; control_reg 420 drivers/i2c/busses/i2c-mt65xx.c mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); control_reg 566 drivers/i2c/busses/i2c-mt65xx.c u16 control_reg; control_reg 582 drivers/i2c/busses/i2c-mt65xx.c control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & control_reg 585 drivers/i2c/busses/i2c-mt65xx.c control_reg |= I2C_CONTROL_RS; control_reg 588 drivers/i2c/busses/i2c-mt65xx.c control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; control_reg 590 drivers/i2c/busses/i2c-mt65xx.c mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); control_reg 1318 drivers/net/ethernet/ti/cpsw.c u32 control_reg; control_reg 1328 drivers/net/ethernet/ti/cpsw.c control_reg = readl(&cpsw->regs->control); control_reg 1329 drivers/net/ethernet/ti/cpsw.c control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP; control_reg 1330 drivers/net/ethernet/ti/cpsw.c writel(control_reg, &cpsw->regs->control); control_reg 357 drivers/power/supply/ds2780_battery.c u8 *control_reg) control_reg 359 drivers/power/supply/ds2780_battery.c return ds2780_read8(dev_info, control_reg, DS2780_CONTROL_REG); control_reg 363 drivers/power/supply/ds2780_battery.c u8 control_reg) control_reg 367 drivers/power/supply/ds2780_battery.c ret = ds2780_write(dev_info, &control_reg, control_reg 448 drivers/power/supply/ds2780_battery.c u8 control_reg; control_reg 453 drivers/power/supply/ds2780_battery.c ret = ds2780_get_control_register(dev_info, &control_reg); control_reg 458 drivers/power/supply/ds2780_battery.c !!(control_reg & DS2780_CONTROL_REG_PMOD)); control_reg 467 drivers/power/supply/ds2780_battery.c u8 control_reg, new_setting; control_reg 472 drivers/power/supply/ds2780_battery.c ret = ds2780_get_control_register(dev_info, &control_reg); control_reg 486 drivers/power/supply/ds2780_battery.c control_reg |= DS2780_CONTROL_REG_PMOD; control_reg 488 drivers/power/supply/ds2780_battery.c control_reg &= ~DS2780_CONTROL_REG_PMOD; control_reg 490 drivers/power/supply/ds2780_battery.c ret = ds2780_set_control_register(dev_info, control_reg); control_reg 359 drivers/power/supply/ds2781_battery.c u8 *control_reg) control_reg 361 drivers/power/supply/ds2781_battery.c return ds2781_read8(dev_info, control_reg, DS2781_CONTROL); control_reg 365 drivers/power/supply/ds2781_battery.c u8 control_reg) control_reg 369 drivers/power/supply/ds2781_battery.c ret = ds2781_write(dev_info, &control_reg, control_reg 450 drivers/power/supply/ds2781_battery.c u8 control_reg; control_reg 455 drivers/power/supply/ds2781_battery.c ret = ds2781_get_control_register(dev_info, &control_reg); control_reg 460 drivers/power/supply/ds2781_battery.c !!(control_reg & DS2781_CONTROL_PMOD)); control_reg 469 drivers/power/supply/ds2781_battery.c u8 control_reg, new_setting; control_reg 474 drivers/power/supply/ds2781_battery.c ret = ds2781_get_control_register(dev_info, &control_reg); control_reg 488 drivers/power/supply/ds2781_battery.c control_reg |= DS2781_CONTROL_PMOD; control_reg 490 drivers/power/supply/ds2781_battery.c control_reg &= ~DS2781_CONTROL_PMOD; control_reg 492 drivers/power/supply/ds2781_battery.c ret = ds2781_set_control_register(dev_info, control_reg); control_reg 166 drivers/regulator/anatop-regulator.c u32 control_reg; control_reg 203 drivers/regulator/anatop-regulator.c ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg); control_reg 247 drivers/regulator/anatop-regulator.c rdesc->vsel_reg = control_reg; control_reg 258 drivers/regulator/anatop-regulator.c if (control_reg && sreg->delay_bit_width) { control_reg 300 drivers/regulator/anatop-regulator.c rdesc->enable_reg = control_reg; control_reg 55 drivers/regulator/as3722-regulator.c u32 control_reg; control_reg 85 drivers/regulator/as3722-regulator.c .control_reg = AS3722_SD0_CONTROL_REG, control_reg 97 drivers/regulator/as3722-regulator.c .control_reg = AS3722_SD1_CONTROL_REG, control_reg 110 drivers/regulator/as3722-regulator.c .control_reg = AS3722_SD23_CONTROL_REG, control_reg 124 drivers/regulator/as3722-regulator.c .control_reg = AS3722_SD23_CONTROL_REG, control_reg 138 drivers/regulator/as3722-regulator.c .control_reg = AS3722_SD4_CONTROL_REG, control_reg 152 drivers/regulator/as3722-regulator.c .control_reg = AS3722_SD5_CONTROL_REG, control_reg 165 drivers/regulator/as3722-regulator.c .control_reg = AS3722_SD6_CONTROL_REG, control_reg 427 drivers/regulator/as3722-regulator.c if (!as3722_reg_lookup[id].control_reg) control_reg 430 drivers/regulator/as3722-regulator.c ret = as3722_read(as3722, as3722_reg_lookup[id].control_reg, &val); control_reg 433 drivers/regulator/as3722-regulator.c as3722_reg_lookup[id].control_reg, ret); control_reg 452 drivers/regulator/as3722-regulator.c if (!as3722_reg_lookup[id].control_reg) control_reg 464 drivers/regulator/as3722-regulator.c ret = as3722_update_bits(as3722, as3722_reg_lookup[id].control_reg, control_reg 468 drivers/regulator/as3722-regulator.c as3722_reg_lookup[id].control_reg, ret); control_reg 105 drivers/regulator/ti-abb-regulator.c void __iomem *control_reg; control_reg 270 drivers/regulator/ti-abb-regulator.c ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, abb->control_reg); control_reg 281 drivers/regulator/ti-abb-regulator.c ti_abb_rmw(regs->opp_change_mask, 1, abb->control_reg); control_reg 725 drivers/regulator/ti-abb-regulator.c abb->control_reg = abb->base + abb->regs->control_off; control_reg 730 drivers/regulator/ti-abb-regulator.c abb->control_reg = devm_ioremap_resource(dev, res); control_reg 731 drivers/regulator/ti-abb-regulator.c if (IS_ERR(abb->control_reg)) control_reg 732 drivers/regulator/ti-abb-regulator.c return PTR_ERR(abb->control_reg); control_reg 15 drivers/scsi/pcmcia/nsp_message.c unsigned char data_reg, control_reg; control_reg 33 drivers/scsi/pcmcia/nsp_message.c control_reg = nsp_index_read(base, SCSIBUSCTRL); control_reg 34 drivers/scsi/pcmcia/nsp_message.c control_reg |= SCSI_ACK; control_reg 35 drivers/scsi/pcmcia/nsp_message.c nsp_index_write(base, SCSIBUSCTRL, control_reg); control_reg 41 drivers/scsi/pcmcia/nsp_message.c control_reg = nsp_index_read(base, SCSIBUSCTRL); control_reg 42 drivers/scsi/pcmcia/nsp_message.c control_reg &= ~SCSI_ACK; control_reg 43 drivers/scsi/pcmcia/nsp_message.c nsp_index_write(base, SCSIBUSCTRL, control_reg); control_reg 437 drivers/soc/fsl/qe/qe_ic.c u32 temp, control_reg = QEIC_CICNR, shift = 0; control_reg 460 drivers/soc/fsl/qe/qe_ic.c control_reg = QEIC_CRICR; control_reg 464 drivers/soc/fsl/qe/qe_ic.c control_reg = QEIC_CRICR; control_reg 471 drivers/soc/fsl/qe/qe_ic.c temp = qe_ic_read(qe_ic->regs, control_reg); control_reg 474 drivers/soc/fsl/qe/qe_ic.c qe_ic_write(qe_ic->regs, control_reg, temp); control_reg 45 drivers/staging/fieldbus/anybuss/arcx-anybus.c u8 control_reg; control_reg 58 drivers/staging/fieldbus/anybuss/arcx-anybus.c cd->control_reg &= ~rst_bit; control_reg 60 drivers/staging/fieldbus/anybuss/arcx-anybus.c cd->control_reg |= rst_bit; control_reg 61 drivers/staging/fieldbus/anybuss/arcx-anybus.c writeb(cd->control_reg, cd->cpld_base + CPLD_CONTROL); control_reg 1416 drivers/tty/serial/pmac_zilog.c uap->control_reg = uap->port.membase; control_reg 1417 drivers/tty/serial/pmac_zilog.c uap->data_reg = uap->control_reg + 0x10; control_reg 1535 drivers/tty/serial/pmac_zilog.c iounmap(uap->control_reg); control_reg 1721 drivers/tty/serial/pmac_zilog.c uap->control_reg = uap->port.membase; control_reg 1722 drivers/tty/serial/pmac_zilog.c uap->data_reg = uap->control_reg + 4; control_reg 55 drivers/tty/serial/pmac_zilog.h volatile u8 __iomem *control_reg; control_reg 88 drivers/tty/serial/pmac_zilog.h writeb(reg, port->control_reg); control_reg 89 drivers/tty/serial/pmac_zilog.h return readb(port->control_reg); control_reg 95 drivers/tty/serial/pmac_zilog.h writeb(reg, port->control_reg); control_reg 96 drivers/tty/serial/pmac_zilog.h writeb(value, port->control_reg); control_reg 111 drivers/tty/serial/pmac_zilog.h (void)readb(port->control_reg); control_reg 45 drivers/watchdog/ts72xx_wdt.c void __iomem *control_reg; control_reg 56 drivers/watchdog/ts72xx_wdt.c writeb(priv->regval, priv->control_reg); control_reg 66 drivers/watchdog/ts72xx_wdt.c writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg); control_reg 134 drivers/watchdog/ts72xx_wdt.c priv->control_reg = devm_platform_ioremap_resource(pdev, 0); control_reg 135 drivers/watchdog/ts72xx_wdt.c if (IS_ERR(priv->control_reg)) control_reg 136 drivers/watchdog/ts72xx_wdt.c return PTR_ERR(priv->control_reg); control_reg 87 include/linux/clk/ti.h struct clk_omap_reg control_reg; control_reg 120 sound/pci/echoaudio/echo3g_dsp.c u32 control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 123 sound/pci/echoaudio/echo3g_dsp.c control_reg |= E3G_PHANTOM_POWER; control_reg 125 sound/pci/echoaudio/echo3g_dsp.c control_reg &= ~E3G_PHANTOM_POWER; control_reg 128 sound/pci/echoaudio/echo3g_dsp.c return write_control_reg(chip, control_reg, control_reg 145 sound/pci/echoaudio/echoaudio_3g.c static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) control_reg 147 sound/pci/echoaudio/echoaudio_3g.c control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; control_reg 151 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; control_reg 155 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_SAMPLE_RATE0; control_reg 158 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_SAMPLE_RATE1; control_reg 163 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_PRO_MODE; control_reg 166 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_NOT_AUDIO; control_reg 168 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | control_reg 171 sound/pci/echoaudio/echoaudio_3g.c return control_reg; control_reg 179 sound/pci/echoaudio/echoaudio_3g.c u32 control_reg; control_reg 181 sound/pci/echoaudio/echoaudio_3g.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 183 sound/pci/echoaudio/echoaudio_3g.c control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate); control_reg 184 sound/pci/echoaudio/echoaudio_3g.c return write_control_reg(chip, control_reg, get_frq_reg(chip), 0); control_reg 260 sound/pci/echoaudio/echoaudio_3g.c u32 control_reg, clock, base_rate, frq_reg; control_reg 278 sound/pci/echoaudio/echoaudio_3g.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 279 sound/pci/echoaudio/echoaudio_3g.c control_reg &= E3G_CLOCK_CLEAR_MASK; control_reg 304 sound/pci/echoaudio/echoaudio_3g.c control_reg |= clock; control_reg 305 sound/pci/echoaudio/echoaudio_3g.c control_reg = set_spdif_bits(chip, control_reg, rate); control_reg 320 sound/pci/echoaudio/echoaudio_3g.c "SetSampleRate: %d clock %x\n", rate, control_reg); control_reg 323 sound/pci/echoaudio/echoaudio_3g.c return write_control_reg(chip, control_reg, frq_reg, 0); control_reg 331 sound/pci/echoaudio/echoaudio_3g.c u32 control_reg, clocks_from_dsp; control_reg 335 sound/pci/echoaudio/echoaudio_3g.c control_reg = le32_to_cpu(chip->comm_page->control_register) & control_reg 346 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_CLOCK; control_reg 348 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_DOUBLE_SPEED_MODE; control_reg 350 sound/pci/echoaudio/echoaudio_3g.c control_reg &= ~E3G_DOUBLE_SPEED_MODE; control_reg 355 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_ADAT_CLOCK; control_reg 356 sound/pci/echoaudio/echoaudio_3g.c control_reg &= ~E3G_DOUBLE_SPEED_MODE; control_reg 359 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_WORD_CLOCK; control_reg 361 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_DOUBLE_SPEED_MODE; control_reg 363 sound/pci/echoaudio/echoaudio_3g.c control_reg &= ~E3G_DOUBLE_SPEED_MODE; control_reg 372 sound/pci/echoaudio/echoaudio_3g.c return write_control_reg(chip, control_reg, get_frq_reg(chip), 1); control_reg 379 sound/pci/echoaudio/echoaudio_3g.c u32 control_reg; control_reg 408 sound/pci/echoaudio/echoaudio_3g.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 409 sound/pci/echoaudio/echoaudio_3g.c control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK; control_reg 414 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_SPDIF_OPTICAL_MODE; control_reg 420 sound/pci/echoaudio/echoaudio_3g.c control_reg |= E3G_ADAT_MODE; control_reg 421 sound/pci/echoaudio/echoaudio_3g.c control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */ control_reg 425 sound/pci/echoaudio/echoaudio_3g.c err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1); control_reg 158 sound/pci/echoaudio/echoaudio_gml.c u32 control_reg; control_reg 162 sound/pci/echoaudio/echoaudio_gml.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 163 sound/pci/echoaudio/echoaudio_gml.c control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; control_reg 166 sound/pci/echoaudio/echoaudio_gml.c control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | control_reg 170 sound/pci/echoaudio/echoaudio_gml.c control_reg |= GML_SPDIF_PRO_MODE; control_reg 174 sound/pci/echoaudio/echoaudio_gml.c control_reg |= GML_SPDIF_SAMPLE_RATE0 | control_reg 178 sound/pci/echoaudio/echoaudio_gml.c control_reg |= GML_SPDIF_SAMPLE_RATE0; control_reg 181 sound/pci/echoaudio/echoaudio_gml.c control_reg |= GML_SPDIF_SAMPLE_RATE1; control_reg 188 sound/pci/echoaudio/echoaudio_gml.c control_reg |= GML_SPDIF_SAMPLE_RATE0 | control_reg 192 sound/pci/echoaudio/echoaudio_gml.c control_reg |= GML_SPDIF_SAMPLE_RATE1; control_reg 197 sound/pci/echoaudio/echoaudio_gml.c if ((err = write_control_reg(chip, control_reg, false))) control_reg 124 sound/pci/echoaudio/gina24_dsp.c u32 control_reg; control_reg 154 sound/pci/echoaudio/gina24_dsp.c control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; control_reg 155 sound/pci/echoaudio/gina24_dsp.c err = write_control_reg(chip, control_reg, true); control_reg 164 sound/pci/echoaudio/gina24_dsp.c u32 control_reg, clock; control_reg 182 sound/pci/echoaudio/gina24_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 183 sound/pci/echoaudio/gina24_dsp.c control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; control_reg 198 sound/pci/echoaudio/gina24_dsp.c if (control_reg & GML_SPDIF_PRO_MODE) control_reg 223 sound/pci/echoaudio/gina24_dsp.c control_reg |= clock; control_reg 229 sound/pci/echoaudio/gina24_dsp.c return write_control_reg(chip, control_reg, false); control_reg 236 sound/pci/echoaudio/gina24_dsp.c u32 control_reg, clocks_from_dsp; control_reg 240 sound/pci/echoaudio/gina24_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register) & control_reg 251 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_SPDIF_CLOCK; control_reg 253 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_DOUBLE_SPEED_MODE; control_reg 255 sound/pci/echoaudio/gina24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 260 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_ADAT_CLOCK; control_reg 261 sound/pci/echoaudio/gina24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 264 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_ESYNC_CLOCK; control_reg 265 sound/pci/echoaudio/gina24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 268 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE; control_reg 277 sound/pci/echoaudio/gina24_dsp.c return write_control_reg(chip, control_reg, true); control_reg 284 sound/pci/echoaudio/gina24_dsp.c u32 control_reg; control_reg 314 sound/pci/echoaudio/gina24_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 315 sound/pci/echoaudio/gina24_dsp.c control_reg &= GML_DIGITAL_MODE_CLEAR_MASK; control_reg 320 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_SPDIF_OPTICAL_MODE; control_reg 325 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_SPDIF_CDROM_MODE; control_reg 331 sound/pci/echoaudio/gina24_dsp.c control_reg |= GML_ADAT_MODE; control_reg 332 sound/pci/echoaudio/gina24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 336 sound/pci/echoaudio/gina24_dsp.c err = write_control_reg(chip, control_reg, true); control_reg 92 sound/pci/echoaudio/indigo_dsp.c u32 control_reg; control_reg 96 sound/pci/echoaudio/indigo_dsp.c control_reg = MIA_96000; control_reg 99 sound/pci/echoaudio/indigo_dsp.c control_reg = MIA_88200; control_reg 102 sound/pci/echoaudio/indigo_dsp.c control_reg = MIA_48000; control_reg 105 sound/pci/echoaudio/indigo_dsp.c control_reg = MIA_44100; control_reg 108 sound/pci/echoaudio/indigo_dsp.c control_reg = MIA_32000; control_reg 117 sound/pci/echoaudio/indigo_dsp.c if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { control_reg 122 sound/pci/echoaudio/indigo_dsp.c chip->comm_page->control_register = cpu_to_le32(control_reg); control_reg 31 sound/pci/echoaudio/indigo_express_dsp.c u32 clock, control_reg, old_control_reg; control_reg 37 sound/pci/echoaudio/indigo_express_dsp.c control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; control_reg 62 sound/pci/echoaudio/indigo_express_dsp.c control_reg |= clock; control_reg 63 sound/pci/echoaudio/indigo_express_dsp.c if (control_reg != old_control_reg) { control_reg 66 sound/pci/echoaudio/indigo_express_dsp.c chip->comm_page->control_register = cpu_to_le32(control_reg); control_reg 92 sound/pci/echoaudio/indigodj_dsp.c u32 control_reg; control_reg 96 sound/pci/echoaudio/indigodj_dsp.c control_reg = MIA_96000; control_reg 99 sound/pci/echoaudio/indigodj_dsp.c control_reg = MIA_88200; control_reg 102 sound/pci/echoaudio/indigodj_dsp.c control_reg = MIA_48000; control_reg 105 sound/pci/echoaudio/indigodj_dsp.c control_reg = MIA_44100; control_reg 108 sound/pci/echoaudio/indigodj_dsp.c control_reg = MIA_32000; control_reg 117 sound/pci/echoaudio/indigodj_dsp.c if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { control_reg 122 sound/pci/echoaudio/indigodj_dsp.c chip->comm_page->control_register = cpu_to_le32(control_reg); control_reg 159 sound/pci/echoaudio/layla24_dsp.c u32 control_reg, clock, base_rate; control_reg 176 sound/pci/echoaudio/layla24_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 177 sound/pci/echoaudio/layla24_dsp.c control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; control_reg 194 sound/pci/echoaudio/layla24_dsp.c if (control_reg & GML_SPDIF_PRO_MODE) control_reg 219 sound/pci/echoaudio/layla24_dsp.c control_reg |= GML_DOUBLE_SPEED_MODE; control_reg 237 sound/pci/echoaudio/layla24_dsp.c control_reg |= clock; control_reg 242 sound/pci/echoaudio/layla24_dsp.c "set_sample_rate: %d clock %d\n", rate, control_reg); control_reg 244 sound/pci/echoaudio/layla24_dsp.c return write_control_reg(chip, control_reg, false); control_reg 251 sound/pci/echoaudio/layla24_dsp.c u32 control_reg, clocks_from_dsp; control_reg 254 sound/pci/echoaudio/layla24_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register) & control_reg 266 sound/pci/echoaudio/layla24_dsp.c control_reg |= GML_SPDIF_CLOCK; control_reg 268 sound/pci/echoaudio/layla24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 271 sound/pci/echoaudio/layla24_dsp.c control_reg |= GML_WORD_CLOCK; control_reg 273 sound/pci/echoaudio/layla24_dsp.c control_reg |= GML_DOUBLE_SPEED_MODE; control_reg 275 sound/pci/echoaudio/layla24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 280 sound/pci/echoaudio/layla24_dsp.c control_reg |= GML_ADAT_CLOCK; control_reg 281 sound/pci/echoaudio/layla24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 290 sound/pci/echoaudio/layla24_dsp.c return write_control_reg(chip, control_reg, true); control_reg 332 sound/pci/echoaudio/layla24_dsp.c u32 control_reg; control_reg 370 sound/pci/echoaudio/layla24_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 371 sound/pci/echoaudio/layla24_dsp.c control_reg &= GML_DIGITAL_MODE_CLEAR_MASK; control_reg 375 sound/pci/echoaudio/layla24_dsp.c control_reg |= GML_SPDIF_OPTICAL_MODE; control_reg 381 sound/pci/echoaudio/layla24_dsp.c control_reg |= GML_ADAT_MODE; control_reg 382 sound/pci/echoaudio/layla24_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 386 sound/pci/echoaudio/layla24_dsp.c err = write_control_reg(chip, control_reg, true); control_reg 109 sound/pci/echoaudio/mia_dsp.c u32 control_reg; control_reg 113 sound/pci/echoaudio/mia_dsp.c control_reg = MIA_96000; control_reg 116 sound/pci/echoaudio/mia_dsp.c control_reg = MIA_88200; control_reg 119 sound/pci/echoaudio/mia_dsp.c control_reg = MIA_48000; control_reg 122 sound/pci/echoaudio/mia_dsp.c control_reg = MIA_44100; control_reg 125 sound/pci/echoaudio/mia_dsp.c control_reg = MIA_32000; control_reg 135 sound/pci/echoaudio/mia_dsp.c control_reg |= MIA_SPDIF; control_reg 138 sound/pci/echoaudio/mia_dsp.c if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { control_reg 143 sound/pci/echoaudio/mia_dsp.c chip->comm_page->control_register = cpu_to_le32(control_reg); control_reg 117 sound/pci/echoaudio/mona_dsp.c u32 control_reg; control_reg 150 sound/pci/echoaudio/mona_dsp.c control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; control_reg 151 sound/pci/echoaudio/mona_dsp.c err = write_control_reg(chip, control_reg, true); control_reg 198 sound/pci/echoaudio/mona_dsp.c u32 control_reg, clock; control_reg 244 sound/pci/echoaudio/mona_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 245 sound/pci/echoaudio/mona_dsp.c control_reg &= GML_CLOCK_CLEAR_MASK; control_reg 246 sound/pci/echoaudio/mona_dsp.c control_reg &= GML_SPDIF_RATE_CLEAR_MASK; control_reg 261 sound/pci/echoaudio/mona_dsp.c if (control_reg & GML_SPDIF_PRO_MODE) control_reg 286 sound/pci/echoaudio/mona_dsp.c control_reg |= clock; control_reg 293 sound/pci/echoaudio/mona_dsp.c return write_control_reg(chip, control_reg, force_write); control_reg 300 sound/pci/echoaudio/mona_dsp.c u32 control_reg, clocks_from_dsp; control_reg 309 sound/pci/echoaudio/mona_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register) & control_reg 326 sound/pci/echoaudio/mona_dsp.c control_reg |= GML_SPDIF_CLOCK; control_reg 328 sound/pci/echoaudio/mona_dsp.c control_reg |= GML_DOUBLE_SPEED_MODE; control_reg 330 sound/pci/echoaudio/mona_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 339 sound/pci/echoaudio/mona_dsp.c control_reg |= GML_WORD_CLOCK; control_reg 341 sound/pci/echoaudio/mona_dsp.c control_reg |= GML_DOUBLE_SPEED_MODE; control_reg 343 sound/pci/echoaudio/mona_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 349 sound/pci/echoaudio/mona_dsp.c control_reg |= GML_ADAT_CLOCK; control_reg 350 sound/pci/echoaudio/mona_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 359 sound/pci/echoaudio/mona_dsp.c return write_control_reg(chip, control_reg, true); control_reg 366 sound/pci/echoaudio/mona_dsp.c u32 control_reg; control_reg 395 sound/pci/echoaudio/mona_dsp.c control_reg = le32_to_cpu(chip->comm_page->control_register); control_reg 396 sound/pci/echoaudio/mona_dsp.c control_reg &= GML_DIGITAL_MODE_CLEAR_MASK; control_reg 401 sound/pci/echoaudio/mona_dsp.c control_reg |= GML_SPDIF_OPTICAL_MODE; control_reg 413 sound/pci/echoaudio/mona_dsp.c control_reg |= GML_ADAT_MODE; control_reg 414 sound/pci/echoaudio/mona_dsp.c control_reg &= ~GML_DOUBLE_SPEED_MODE; control_reg 418 sound/pci/echoaudio/mona_dsp.c err = write_control_reg(chip, control_reg, false);