control_offset    244 drivers/input/rmi4/rmi_f12.c 	u16 control_offset = 0;
control_offset    251 drivers/input/rmi4/rmi_f12.c 			control_offset = rmi_register_desc_calc_reg_offset(
control_offset    263 drivers/input/rmi4/rmi_f12.c 					+ control_offset, buf, control_size);
control_offset    283 drivers/input/rmi4/rmi_f12.c 				fn->fd.control_base_addr + control_offset,
control_offset     58 drivers/mfd/twl4030-irq.c 	u8	control_offset;		/* for SIH_CTRL */
control_offset     82 drivers/mfd/twl4030-irq.c 	.control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
control_offset    112 drivers/mfd/twl4030-irq.c 		.control_offset	= REG_GPIO_SIH_CTRL,
control_offset    136 drivers/mfd/twl4030-irq.c 		.control_offset	= TWL4030_INTERRUPTS_BCISIHCTRL,
control_offset    172 drivers/mfd/twl4030-irq.c 		.control_offset	= REG_GPIO_SIH_CTRL,
control_offset    196 drivers/mfd/twl4030-irq.c 		.control_offset	= TWL5031_INTERRUPTS_BCISIHCTRL,
control_offset    245 drivers/mfd/twl4030-irq.c 		.control_offset	= TWL5031_ACCSIHCTRL,
control_offset    356 drivers/mfd/twl4030-irq.c 					sih->control_offset);
control_offset    148 drivers/staging/greybus/audio_codec.h 	unsigned long control_offset;
control_offset   1337 drivers/staging/greybus/audio_topology.c 	module->control_offset = module->dai_offset +
control_offset   1339 drivers/staging/greybus/audio_topology.c 	module->widget_offset = module->control_offset +
control_offset   1346 drivers/staging/greybus/audio_topology.c 		module->control_offset);
control_offset   1373 drivers/staging/greybus/audio_topology.c 	controls = (struct gb_audio_control *)module->control_offset;