control1           46 arch/mips/oprofile/op_model_loongson3.c 	unsigned int control1;
control1           64 arch/mips/oprofile/op_model_loongson3.c 	unsigned int control1 = 0;
control1           72 arch/mips/oprofile/op_model_loongson3.c 		control1 |= LOONGSON3_PERFCTRL_EVENT(0, ctr[0].event) |
control1           75 arch/mips/oprofile/op_model_loongson3.c 			control1 |= LOONGSON3_PERFCTRL_KERNEL;
control1           77 arch/mips/oprofile/op_model_loongson3.c 			control1 |= LOONGSON3_PERFCTRL_USER;
control1           92 arch/mips/oprofile/op_model_loongson3.c 		control1 |= LOONGSON3_PERFCTRL_EXL;
control1           96 arch/mips/oprofile/op_model_loongson3.c 	reg.control1 = control1;
control1          116 arch/mips/oprofile/op_model_loongson3.c 	reg.control1 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M);
control1          120 arch/mips/oprofile/op_model_loongson3.c 		write_c0_perflo1(reg.control1);
control1          173 arch/mips/oprofile/op_model_loongson3.c 	write_c0_perflo1(reg.control1);
control1          336 drivers/crypto/inside-secure/safexcel.h 	u32 control1;
control1          534 drivers/crypto/inside-secure/safexcel.h 	u32 control1;
control1          415 drivers/crypto/inside-secure/safexcel_cipher.c 	cdesc->control_data.control1 = ctx->mode;
control1          146 drivers/crypto/inside-secure/safexcel_hash.c 			cdesc->control_data.control1 |=
control1           49 drivers/crypto/mxs-dcp.c 	uint32_t	control1;
control1          249 drivers/crypto/mxs-dcp.c 	desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
control1          252 drivers/crypto/mxs-dcp.c 		desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
control1          254 drivers/crypto/mxs-dcp.c 		desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
control1          575 drivers/crypto/mxs-dcp.c 	desc->control1 = actx->alg;
control1         5266 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 	u16 control1;
control1         5273 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 			  &control1);
control1         5274 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 	control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
control1         5276 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 	control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
control1         5282 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c 			  control1);
control1          208 drivers/net/wireless/broadcom/b43/dma.c 	desc->dma64.control1 = cpu_to_le32(ctl1);
control1          145 drivers/net/wireless/broadcom/b43/dma.h 	__le32 control1;
control1         4465 drivers/net/wireless/marvell/mwl8k.c 	__le16	control1;
control1          358 drivers/regulator/max8973-regulator.c 	uint8_t	control1 = 0;
control1          368 drivers/regulator/max8973-regulator.c 	control1 = data & MAX8973_RAMP_MASK;
control1          369 drivers/regulator/max8973-regulator.c 	switch (control1) {
control1          385 drivers/regulator/max8973-regulator.c 		control1 |= MAX8973_SNS_ENABLE;
control1          388 drivers/regulator/max8973-regulator.c 		control1 |= MAX8973_NFSR_ENABLE;
control1          391 drivers/regulator/max8973-regulator.c 		control1 |= MAX8973_AD_ENABLE;
control1          394 drivers/regulator/max8973-regulator.c 		control1 |= MAX8973_BIAS_ENABLE;
control1          401 drivers/regulator/max8973-regulator.c 		control1 |= MAX8973_FREQSHIFT_9PER;
control1          448 drivers/regulator/max8973-regulator.c 	ret = regmap_write(max->regmap, MAX8973_CONTROL1, control1);
control1          692 drivers/scsi/gdth.c         outb(0x00,PTR2USHORT(&ha->plx->control1));
control1          900 drivers/scsi/gdth.c         outb(0x03, PTR2USHORT(&ha->plx->control1));
control1          752 drivers/scsi/gdth.h     u8              control1;               /* board interrupts enable */
control1          214 include/linux/amba/pl080.h 	u32	control1;