conf0             184 arch/mips/include/asm/mipsmtregs.h 	unsigned conf0;
conf0             189 arch/mips/include/asm/mipsmtregs.h 	conf0 = read_c0_mvpconf0();
conf0             190 arch/mips/include/asm/mipsmtregs.h 	return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
conf0             402 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c 	u8 threshold, conf0, conf1, ca;
conf0             407 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c 		conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
conf0             415 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c 		conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
conf0             429 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c 	conf0 |= HDMI_AHB_DMA_CONF0_EN_HLOCK;
conf0             434 drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c 	writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);
conf0              43 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 	u8 conf0 = 0;
conf0              58 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 	conf0		= (HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_EN0);
conf0              63 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 		conf0 |= HDMI_AUD_CONF0_I2S_EN3;
conf0              66 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 		conf0 |= HDMI_AUD_CONF0_I2S_EN2;
conf0              69 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 		conf0 |= HDMI_AUD_CONF0_I2S_EN1;
conf0             109 drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c 	hdmi_write(audio, conf0, HDMI_AUD_CONF0);
conf0             598 drivers/gpu/drm/mcde/mcde_display.c 	u32 conf0;
conf0             607 drivers/gpu/drm/mcde/mcde_display.c 		conf0 = MCDE_DSIVID0CONF0;
conf0             616 drivers/gpu/drm/mcde/mcde_display.c 		conf0 = MCDE_DSIVID1CONF0;
conf0             625 drivers/gpu/drm/mcde/mcde_display.c 		conf0 = MCDE_DSIVID2CONF0;
conf0             663 drivers/gpu/drm/mcde/mcde_display.c 	writel(val, mcde->regs + conf0);
conf0            1192 drivers/iio/adc/xilinx-xadc-core.c 	unsigned int conf0;
conf0            1232 drivers/iio/adc/xilinx-xadc-core.c 	ret = xadc_parse_dt(indio_dev, pdev->dev.of_node, &conf0);
conf0            1294 drivers/iio/adc/xilinx-xadc-core.c 	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
conf0              93 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c 	u16 conf0 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
conf0              96 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c 		return !(conf0 & MT_EE_NIC_CONF_0_PA_INT_5G);
conf0              98 drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c 		return !(conf0 & MT_EE_NIC_CONF_0_PA_INT_2G);
conf0              97 drivers/pinctrl/intel/pinctrl-baytrail.c 	u32 conf0;
conf0            1199 drivers/pinctrl/intel/pinctrl-baytrail.c 	u32 conf0, val;
conf0            1220 drivers/pinctrl/intel/pinctrl-baytrail.c 		conf0 = readl(reg);
conf0            1242 drivers/pinctrl/intel/pinctrl-baytrail.c 		switch (conf0 & BYT_PULL_ASSIGN_MASK) {
conf0            1251 drivers/pinctrl/intel/pinctrl-baytrail.c 		switch (conf0 & BYT_PULL_STR_MASK) {
conf0            1274 drivers/pinctrl/intel/pinctrl-baytrail.c 			   conf0 & 0x7,
conf0            1275 drivers/pinctrl/intel/pinctrl-baytrail.c 			   conf0 & BYT_TRIG_NEG ? " fall" : "     ",
conf0            1276 drivers/pinctrl/intel/pinctrl-baytrail.c 			   conf0 & BYT_TRIG_POS ? " rise" : "     ",
conf0            1277 drivers/pinctrl/intel/pinctrl-baytrail.c 			   conf0 & BYT_TRIG_LVL ? " level" : "      ");
conf0            1284 drivers/pinctrl/intel/pinctrl-baytrail.c 		if (conf0 & BYT_IODEN)
conf0            1681 drivers/pinctrl/intel/pinctrl-baytrail.c 		vg->saved_context[i].conf0 = value;
conf0            1714 drivers/pinctrl/intel/pinctrl-baytrail.c 		     vg->saved_context[i].conf0) {
conf0            1716 drivers/pinctrl/intel/pinctrl-baytrail.c 			value |= vg->saved_context[i].conf0;