D4VGA_CONTROL     208 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D4VGA_CONTROL), \
D4VGA_CONTROL     274 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D4VGA_CONTROL), \
D4VGA_CONTROL     327 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D4VGA_CONTROL), \
D4VGA_CONTROL     420 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t D4VGA_CONTROL;
D4VGA_CONTROL     575 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
D4VGA_CONTROL     474 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
D4VGA_CONTROL     483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_WRITE(D4VGA_CONTROL, 0);
D4VGA_CONTROL     176 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_WRITE(D4VGA_CONTROL, 0);