D3VGA_CONTROL     207 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D3VGA_CONTROL), \
D3VGA_CONTROL     273 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D3VGA_CONTROL), \
D3VGA_CONTROL     326 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	SR(D3VGA_CONTROL), \
D3VGA_CONTROL     419 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	uint32_t D3VGA_CONTROL;
D3VGA_CONTROL     574 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 	HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
D3VGA_CONTROL     473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
D3VGA_CONTROL     482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	REG_WRITE(D3VGA_CONTROL, 0);
D3VGA_CONTROL     175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	REG_WRITE(D3VGA_CONTROL, 0);