cntval_mask       917 arch/x86/events/amd/core.c 	.cntval_mask		= (1ULL << 48) - 1,
cntval_mask      1237 arch/x86/events/core.c 	wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
cntval_mask      1246 arch/x86/events/core.c 			(u64)(-left) & x86_pmu.cntval_mask);
cntval_mask      1838 arch/x86/events/core.c 	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
cntval_mask      4559 arch/x86/events/intel/core.c 	x86_pmu.cntval_mask		= (1ULL << eax.split.bit_width) - 1;
cntval_mask      5161 arch/x86/events/intel/core.c 		x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
cntval_mask      1135 arch/x86/events/intel/ds.c 			(u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
cntval_mask       308 arch/x86/events/intel/knc.c 	.cntval_mask		= (1ULL << 40) - 1,
cntval_mask      1322 arch/x86/events/intel/p4.c 	.cntval_mask		= ARCH_P4_CNTRVAL_MASK,
cntval_mask       226 arch/x86/events/intel/p6.c 	.cntval_mask		= (1ULL << 32) - 1,
cntval_mask       591 arch/x86/events/perf_event.h 	u64		cntval_mask;