cntl              182 arch/arm/mach-footbridge/dc21285.c 	unsigned int cntl;
cntl              188 arch/arm/mach-footbridge/dc21285.c 	cntl = *CSR_SA110_CNTL & 0xffffdf07;
cntl              189 arch/arm/mach-footbridge/dc21285.c 	*CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
cntl               91 arch/arm/mach-integrator/impd1.c 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
cntl              119 arch/arm/mach-integrator/impd1.c 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
cntl              147 arch/arm/mach-integrator/impd1.c 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
cntl              179 arch/arm/mach-integrator/impd1.c 	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
cntl               22 arch/arm/mach-omap1/include/mach/mtd-xip.h 	u32 cntl;			/* CNTL_TIMER, R/W */
cntl               63 arch/arm/mach-omap1/time.c 	u32 cntl;			/* CNTL_TIMER, R/W */
cntl               82 arch/arm/mach-omap1/time.c 	writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
cntl               89 arch/arm/mach-omap1/time.c 	writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
cntl              101 arch/arm/mach-omap1/time.c 	writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
cntl              105 arch/arm/mach-omap1/time.c 	writel(timerflags, &timer->cntl);
cntl              112 arch/arm/mach-omap1/time.c 	writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
cntl              126 arch/powerpc/platforms/cell/spufs/context.c 	if (ctx->cntl)
cntl              127 arch/powerpc/platforms/cell/spufs/context.c 		unmap_mapping_range(ctx->cntl, 0, SPUFS_CNTL_MAP_SIZE, 1);
cntl              423 arch/powerpc/platforms/cell/spufs/file.c 		ctx->cntl = inode->i_mapping;
cntl              439 arch/powerpc/platforms/cell/spufs/file.c 		ctx->cntl = NULL;
cntl               73 arch/powerpc/platforms/cell/spufs/spufs.h 	struct address_space *cntl;	   /* 'control' area mappings. */
cntl              681 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	union TCP_WATCH_CNTL_BITS cntl;
cntl              684 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	cntl.u32All = 0;
cntl              686 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	cntl.bitfields.valid = 0;
cntl              687 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
cntl              688 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	cntl.bitfields.atc = 1;
cntl              693 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 			ADDRESS_WATCH_REG_CNTL], cntl.u32All);
cntl              705 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	union TCP_WATCH_CNTL_BITS cntl;
cntl              707 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	cntl.u32All = cntl_val;
cntl              710 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	cntl.bitfields.valid = 0;
cntl              712 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 		ADDRESS_WATCH_REG_CNTL], cntl.u32All);
cntl              721 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	cntl.bitfields.valid = 1;
cntl              724 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 		ADDRESS_WATCH_REG_CNTL], cntl.u32All);
cntl              403 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 			WREG32_SMC(local_cac_reg->cntl, data);
cntl               85 drivers/gpu/drm/amd/amdgpu/kv_dpm.h 	u32 cntl;
cntl              233 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 			union TCP_WATCH_CNTL_BITS *cntl,
cntl              241 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	cntl->u32All = 0;
cntl              244 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		cntl->bitfields.mask =
cntl              248 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
cntl              257 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	cntl->bitfields.mode = adw_info->watch_mode[index];
cntl              258 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	cntl->bitfields.vmid = (uint32_t) vmid;
cntl              260 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT;
cntl              262 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);
cntl              274 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	union TCP_WATCH_CNTL_BITS cntl;
cntl              288 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	cntl.u32All = 0;
cntl              303 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 						&cntl, i, pdd->qpd.vmid);
cntl              315 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.mask);
cntl              317 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.mode);
cntl              319 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.vmid);
cntl              321 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.atc);
cntl              327 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 						cntl.u32All,
cntl              341 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	union TCP_WATCH_CNTL_BITS cntl;
cntl              353 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 	cntl.u32All = 0;
cntl              396 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 						&cntl,
cntl              412 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.mask);
cntl              414 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.mode);
cntl              416 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.vmid);
cntl              418 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 				cntl.bitfields.atc);
cntl              430 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		packets_vec[0].reg_data[0] = cntl.u32All;
cntl              454 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 			cntl.bitfields.valid = 1;
cntl              456 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 			cntl.bitfields.valid = 0;
cntl              466 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c 		packets_vec[3].reg_data[0] = cntl.u32All;
cntl              728 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 	struct bp_transmitter_control *cntl)
cntl              735 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 	return bp->cmd_tbl.transmitter_control(bp, cntl);
cntl              740 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 	struct bp_encoder_control *cntl)
cntl              747 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
cntl             1019 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 	struct bp_transmitter_control *cntl)
cntl             1026 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 	return bp->cmd_tbl.transmitter_control(bp, cntl);
cntl             1031 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 	struct bp_encoder_control *cntl)
cntl             1038 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
cntl              106 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl);
cntl              110 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl);
cntl              114 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl);
cntl              143 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl);
cntl              146 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl);
cntl              149 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl);
cntl              170 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl)
cntl              175 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (cntl != NULL)
cntl              176 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		switch (cntl->engine_id) {
cntl              180 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cmd_tbl->encoder_control_dig1(bp, cntl);
cntl              185 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cmd_tbl->encoder_control_dig2(bp, cntl);
cntl              197 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl)
cntl              202 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
cntl              212 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl)
cntl              217 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
cntl              227 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl)
cntl              232 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (LANE_COUNT_FOUR < cntl->lanes_number)
cntl              237 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
cntl              240 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
cntl              241 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
cntl              244 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cntl->signal,
cntl              245 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cntl->enable_dp_audio);
cntl              246 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
cntl              256 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl)
cntl              261 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (LANE_COUNT_FOUR < cntl->lanes_number)
cntl              266 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
cntl              269 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
cntl              270 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
cntl              273 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cntl->signal,
cntl              274 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cntl->enable_dp_audio));
cntl              275 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
cntl              285 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_encoder_control *cntl)
cntl              290 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucDigId = (uint8_t)(cntl->engine_id);
cntl              291 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
cntl              293 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ulPixelClock = cntl->pixel_clock / 10;
cntl              296 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cntl->signal,
cntl              297 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cntl->enable_dp_audio));
cntl              298 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
cntl              300 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->color_depth) {
cntl              317 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
cntl              318 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		switch (cntl->color_depth) {
cntl              351 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl);
cntl              354 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl);
cntl              357 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl);
cntl              360 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl);
cntl              363 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl);
cntl              398 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl)
cntl              403 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
cntl              407 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->transmitter) {
cntl              420 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->action) {
cntl              434 drivers/gpu/drm/amd/display/dc/bios/command_table.c 				cpu_to_le16((uint8_t)cntl->connector_obj_id.id);
cntl              438 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
cntl              439 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
cntl              443 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		if (LANE_COUNT_FOUR < cntl->lanes_number) {
cntl              456 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
cntl              462 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
cntl              470 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.acConfig.fCoherentMode = cntl->coherent;
cntl              472 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
cntl              473 drivers/gpu/drm/amd/display/dc/bios/command_table.c 			|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
cntl              474 drivers/gpu/drm/amd/display/dc/bios/command_table.c 			|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
cntl              483 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (ENGINE_ID_DIGB == cntl->engine_id)
cntl              506 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cntl->transmitter);
cntl              508 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = (uint8_t)cntl->action;
cntl              518 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl)
cntl              524 drivers/gpu/drm/amd/display/dc/bios/command_table.c 			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
cntl              531 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->transmitter) {
cntl              544 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (!cmd->clock_source_id_to_atom(cntl->pll_id, &pll_id))
cntl              548 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->action) {
cntl              562 drivers/gpu/drm/amd/display/dc/bios/command_table.c 				cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
cntl              566 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
cntl              567 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
cntl              570 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		if (dual_link_conn && cntl->multi_path)
cntl              580 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		if (LANE_COUNT_FOUR < cntl->lanes_number) {
cntl              593 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
cntl              599 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
cntl              608 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.acConfig.fCoherentMode = cntl->coherent;
cntl              610 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
cntl              611 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
cntl              612 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
cntl              621 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (ENGINE_ID_DIGB == cntl->engine_id)
cntl              636 drivers/gpu/drm/amd/display/dc/bios/command_table.c 			(uint8_t)cmd->transmitter_bp_to_atom(cntl->transmitter);
cntl              638 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucLaneNum = (uint8_t)cntl->lanes_number;
cntl              642 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = (uint8_t)cntl->action;
cntl              652 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl)
cntl              658 drivers/gpu/drm/amd/display/dc/bios/command_table.c 			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
cntl              663 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->transmitter) {
cntl              676 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (!cmd->clock_source_id_to_ref_clk_src(cntl->pll_id, &ref_clk_src_id))
cntl              679 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->action) {
cntl              694 drivers/gpu/drm/amd/display/dc/bios/command_table.c 				cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
cntl              699 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.asMode.ucLaneSel = (uint8_t)(cntl->lane_select);
cntl              700 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings);
cntl              714 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		if (LANE_COUNT_FOUR < cntl->lanes_number)
cntl              719 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
cntl              725 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
cntl              734 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.acConfig.fCoherentMode = cntl->coherent;
cntl              736 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
cntl              737 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
cntl              738 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
cntl              747 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (ENGINE_ID_DIGB == cntl->engine_id)
cntl              762 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		(uint8_t)(cmd->transmitter_bp_to_atom(cntl->transmitter));
cntl              763 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
cntl              765 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = (uint8_t)(cntl->action);
cntl              775 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl)
cntl              782 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
cntl              783 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = (uint8_t)cntl->action;
cntl              784 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucLaneNum = (uint8_t)cntl->lanes_number;
cntl              785 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;
cntl              788 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		cmd->signal_type_to_atom_dig_mode(cntl->signal);
cntl              790 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		cmd->clock_source_id_to_atom_phy_clk_src_id(cntl->pll_id);
cntl              792 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.asConfig.ucCoherentMode = cntl->coherent;
cntl              794 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		cmd->hpd_sel_to_atom(cntl->hpd_sel);
cntl              796 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		cmd->dig_encoder_sel_to_atom(cntl->engine_id);
cntl              797 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucDPLaneSet = (uint8_t) cntl->lane_settings;
cntl              798 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.usSymClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
cntl              809 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if  (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
cntl              810 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		switch (cntl->color_depth) {
cntl              836 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_transmitter_control *cntl)
cntl              843 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
cntl              844 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucAction = (uint8_t)cntl->action;
cntl              846 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
cntl              847 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.ucDPLaneSet = (uint8_t)cntl->lane_settings;
cntl              849 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		params.ucDigMode = cmd->signal_type_to_atom_dig_mode(cntl->signal);
cntl              851 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucLaneNum = (uint8_t)cntl->lanes_number;
cntl              852 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucHPDSel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
cntl              853 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucDigEncoderSel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
cntl              854 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;
cntl              855 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	params.ulSymClock = cntl->pixel_clock/10;
cntl              867 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->signal) {
cntl              869 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		switch (cntl->color_depth) {
cntl             2111 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_external_encoder_control *cntl);
cntl             2129 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	struct bp_external_encoder_control *cntl)
cntl             2143 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	encoder = cntl->encoder_id;
cntl             2172 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	switch (cntl->action) {
cntl             2177 drivers/gpu/drm/amd/display/dc/bios/command_table.c 				cpu_to_le16((uint16_t)cntl->connector_obj_id.id);
cntl             2186 drivers/gpu/drm/amd/display/dc/bios/command_table.c 				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
cntl             2191 drivers/gpu/drm/amd/display/dc/bios/command_table.c 						cntl->signal, false);
cntl             2196 drivers/gpu/drm/amd/display/dc/bios/command_table.c 			if (LINK_RATE_HIGH == cntl->link_rate)
cntl             2202 drivers/gpu/drm/amd/display/dc/bios/command_table.c 					(uint8_t)(cntl->color_depth);
cntl             2206 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number);
cntl             2210 drivers/gpu/drm/amd/display/dc/bios/command_table.c 				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
cntl             2213 drivers/gpu/drm/amd/display/dc/bios/command_table.c 						cntl->signal, false);
cntl             2214 drivers/gpu/drm/amd/display/dc/bios/command_table.c 		cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number;
cntl             2220 drivers/gpu/drm/amd/display/dc/bios/command_table.c 	cntl_params->ucAction = (uint8_t)cntl->action;
cntl               87 drivers/gpu/drm/amd/display/dc/bios/command_table.h 			struct bp_external_encoder_control *cntl);
cntl               88 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	struct bp_encoder_control *cntl);
cntl              108 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	struct bp_encoder_control *cntl)
cntl              113 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	params.digid = (uint8_t)(cntl->engine_id);
cntl              114 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action);
cntl              116 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	params.pclk_10khz = cntl->pixel_clock / 10;
cntl              119 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 					cntl->signal,
cntl              120 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 					cntl->enable_dp_audio));
cntl              121 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	params.lanenum = (uint8_t)(cntl->lanes_number);
cntl              123 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	switch (cntl->color_depth) {
cntl              140 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
cntl              141 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 		switch (cntl->color_depth) {
cntl              174 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	struct bp_transmitter_control *cntl);
cntl              196 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	struct bp_transmitter_control *cntl)
cntl              202 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter);
cntl              203 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	ps.param.action = (uint8_t)cntl->action;
cntl              205 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
cntl              206 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 		ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;
cntl              209 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 				cmd->signal_type_to_atom_dig_mode(cntl->signal);
cntl              211 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	ps.param.lanenum = (uint8_t)cntl->lanes_number;
cntl              212 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
cntl              213 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
cntl              214 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id;
cntl              215 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	ps.param.symclk_10khz = cntl->pixel_clock/10;
cntl              218 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
cntl              219 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 		cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
cntl              220 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 		cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
cntl              535 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	struct bp_external_encoder_control *cntl);
cntl              553 drivers/gpu/drm/amd/display/dc/bios/command_table2.c 	struct bp_external_encoder_control *cntl)
cntl               87 drivers/gpu/drm/amd/display/dc/bios/command_table2.h 			struct bp_external_encoder_control *cntl);
cntl               97 drivers/gpu/drm/amd/display/dc/dc_bios_types.h 		struct bp_encoder_control *cntl);
cntl              100 drivers/gpu/drm/amd/display/dc/dc_bios_types.h 		struct bp_transmitter_control *cntl);
cntl              126 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control *cntl)
cntl              131 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	result = bp->funcs->transmitter_control(bp, cntl);
cntl              830 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl              833 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_INIT;
cntl              834 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl              835 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.transmitter = enc110->base.transmitter;
cntl              836 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.connector_obj_id = enc110->base.connector;
cntl              837 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.lanes_number = LANE_COUNT_FOUR;
cntl              838 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.coherent = false;
cntl              839 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.hpd_sel = enc110->base.hpd_source;
cntl              842 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		cntl.signal = SIGNAL_TYPE_EDP;
cntl              844 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	result = link_transmitter_control(enc110, &cntl);
cntl              854 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
cntl              856 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		result = link_transmitter_control(enc110, &cntl);
cntl              923 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl              927 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.connector_obj_id = enc110->base.connector;
cntl              928 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
cntl              929 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.engine_id = enc->preferred_engine;
cntl              930 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.transmitter = enc110->base.transmitter;
cntl              931 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pll_id = clock_source;
cntl              932 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.signal = signal;
cntl              933 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
cntl              934 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		cntl.lanes_number = 8;
cntl              936 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		cntl.lanes_number = 4;
cntl              938 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.hpd_sel = enc110->base.hpd_source;
cntl              940 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pixel_clock = pixel_clock;
cntl              941 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.color_depth = color_depth;
cntl              943 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	result = link_transmitter_control(enc110, &cntl);
cntl              959 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl              963 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.connector_obj_id = enc110->base.connector;
cntl              964 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
cntl              965 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.engine_id = enc->preferred_engine;
cntl              966 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.transmitter = enc110->base.transmitter;
cntl              967 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pll_id = clock_source;
cntl              968 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.signal = SIGNAL_TYPE_LVDS;
cntl              969 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.lanes_number = 4;
cntl              971 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.hpd_sel = enc110->base.hpd_source;
cntl              973 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pixel_clock = pixel_clock;
cntl              975 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	result = link_transmitter_control(enc110, &cntl);
cntl              991 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl             1001 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.connector_obj_id = enc110->base.connector;
cntl             1002 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
cntl             1003 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.engine_id = enc->preferred_engine;
cntl             1004 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.transmitter = enc110->base.transmitter;
cntl             1005 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pll_id = clock_source;
cntl             1006 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
cntl             1007 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.lanes_number = link_settings->lane_count;
cntl             1008 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.hpd_sel = enc110->base.hpd_source;
cntl             1009 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pixel_clock = link_settings->link_rate
cntl             1012 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
cntl             1014 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	result = link_transmitter_control(enc110, &cntl);
cntl             1030 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl             1041 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
cntl             1042 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl             1043 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.transmitter = enc110->base.transmitter;
cntl             1044 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pll_id = clock_source;
cntl             1045 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
cntl             1046 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.lanes_number = link_settings->lane_count;
cntl             1047 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.hpd_sel = enc110->base.hpd_source;
cntl             1048 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pixel_clock = link_settings->link_rate
cntl             1051 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
cntl             1053 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	result = link_transmitter_control(enc110, &cntl);
cntl             1070 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl             1088 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_DISABLE;
cntl             1089 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.transmitter = enc110->base.transmitter;
cntl             1090 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.hpd_sel = enc110->base.hpd_source;
cntl             1091 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.signal = signal;
cntl             1092 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.connector_obj_id = enc110->base.connector;
cntl             1094 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	result = link_transmitter_control(enc110, &cntl);
cntl             1115 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl             1122 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
cntl             1123 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.transmitter = enc110->base.transmitter;
cntl             1124 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.connector_obj_id = enc110->base.connector;
cntl             1125 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.lanes_number = link_settings->link_settings.lane_count;
cntl             1126 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.hpd_sel = enc110->base.hpd_source;
cntl             1127 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 	cntl.pixel_clock = link_settings->link_settings.link_rate *
cntl             1147 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		cntl.lane_select = lane;
cntl             1148 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		cntl.lane_settings = training_lane_set.raw;
cntl             1151 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 		link_transmitter_control(enc110, &cntl);
cntl              558 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	struct bp_encoder_control cntl = {0};
cntl              560 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.action = ENCODER_CONTROL_SETUP;
cntl              561 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.engine_id = enc110->base.id;
cntl              562 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
cntl              563 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.enable_dp_audio = enable_audio;
cntl              564 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.pixel_clock = actual_pix_clk_khz;
cntl              565 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.lanes_number = LANE_COUNT_FOUR;
cntl              568 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			enc110->base.bp, &cntl) != BP_RESULT_OK)
cntl              671 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	struct bp_encoder_control cntl = {0};
cntl              673 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.action = ENCODER_CONTROL_SETUP;
cntl              674 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.engine_id = enc110->base.id;
cntl              675 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.signal = is_dual_link ?
cntl              677 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.enable_dp_audio = false;
cntl              678 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
cntl              679 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
cntl              682 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			enc110->base.bp, &cntl) != BP_RESULT_OK)
cntl              696 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	struct bp_encoder_control cntl = {0};
cntl              698 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.action = ENCODER_CONTROL_SETUP;
cntl              699 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.engine_id = enc110->base.id;
cntl              700 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.signal = SIGNAL_TYPE_LVDS;
cntl              701 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.enable_dp_audio = false;
cntl              702 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
cntl              703 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	cntl.lanes_number = LANE_COUNT_FOUR;
cntl              706 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			enc110->base.bp, &cntl) != BP_RESULT_OK)
cntl               80 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 	enum bp_pipe_control_action cntl;
cntl               84 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 		cntl = ASIC_PIPE_INIT;
cntl               86 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 		cntl = ASIC_PIPE_ENABLE;
cntl               88 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 		cntl = ASIC_PIPE_DISABLE;
cntl               93 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c 						dcb, controller_id + 1, cntl);
cntl              199 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	enum bp_pipe_control_action cntl;
cntl              207 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl = ASIC_PIPE_INIT;
cntl              209 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl = ASIC_PIPE_ENABLE;
cntl              211 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl = ASIC_PIPE_DISABLE;
cntl              219 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 						dcb, controller_id + 1, cntl);
cntl              721 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct bp_transmitter_control *cntl)
cntl              725 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	result = bios->funcs->transmitter_control(bios, cntl);
cntl              808 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct bp_transmitter_control cntl = { 0 };
cntl              852 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl.action = power_up ?
cntl              855 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl.transmitter = link->link_enc->transmitter;
cntl              856 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl.connector_obj_id = link->link_enc->connector;
cntl              857 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl.coherent = false;
cntl              858 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl.lanes_number = LANE_COUNT_FOUR;
cntl              859 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		cntl.hpd_sel = link->link_enc->hpd_source;
cntl              860 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
cntl              890 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct bp_transmitter_control cntl = { 0 };
cntl              911 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	cntl.action = enable ?
cntl              916 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	cntl.transmitter = link->link_enc->transmitter;
cntl              917 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	cntl.connector_obj_id = link->link_enc->connector;
cntl              919 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	cntl.lanes_number = LANE_COUNT_FOUR;
cntl              920 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	cntl.hpd_sel = link->link_enc->hpd_source;
cntl              921 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	cntl.signal = SIGNAL_TYPE_EDP;
cntl              935 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
cntl              937 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	link_transmitter_control(ctx->dc_bios, &cntl);
cntl              939 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
cntl              120 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 	enum bp_pipe_control_action cntl;
cntl              127 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 		cntl = ASIC_PIPE_INIT;
cntl              129 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 		cntl = ASIC_PIPE_ENABLE;
cntl              131 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 		cntl = ASIC_PIPE_DISABLE;
cntl              136 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c 						dcb, controller_id + 1, cntl);
cntl              159 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 	enum bp_pipe_control_action cntl;
cntl              166 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		cntl = ASIC_PIPE_INIT;
cntl              168 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		cntl = ASIC_PIPE_ENABLE;
cntl              170 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 		cntl = ASIC_PIPE_DISABLE;
cntl              175 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 						dcb, controller_id + 1, cntl);
cntl               98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	struct bp_transmitter_control *cntl)
cntl              103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	result = bp->funcs->transmitter_control(bp, cntl);
cntl              823 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl              826 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_INIT;
cntl              827 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl              828 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.transmitter = enc10->base.transmitter;
cntl              829 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.connector_obj_id = enc10->base.connector;
cntl              830 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.lanes_number = LANE_COUNT_FOUR;
cntl              831 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.coherent = false;
cntl              832 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.hpd_sel = enc10->base.hpd_source;
cntl              835 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		cntl.signal = SIGNAL_TYPE_EDP;
cntl              837 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	result = link_transmitter_control(enc10, &cntl);
cntl              847 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
cntl              849 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		result = link_transmitter_control(enc10, &cntl);
cntl              917 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl              922 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
cntl              923 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.engine_id = enc->preferred_engine;
cntl              924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.transmitter = enc10->base.transmitter;
cntl              925 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.pll_id = clock_source;
cntl              926 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.signal = signal;
cntl              927 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
cntl              928 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		cntl.lanes_number = 8;
cntl              930 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		cntl.lanes_number = 4;
cntl              932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.hpd_sel = enc10->base.hpd_source;
cntl              934 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.pixel_clock = pixel_clock;
cntl              935 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.color_depth = color_depth;
cntl              937 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	result = link_transmitter_control(enc10, &cntl);
cntl              953 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl              964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
cntl              965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.engine_id = enc->preferred_engine;
cntl              966 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.transmitter = enc10->base.transmitter;
cntl              967 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.pll_id = clock_source;
cntl              968 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
cntl              969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.lanes_number = link_settings->lane_count;
cntl              970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.hpd_sel = enc10->base.hpd_source;
cntl              971 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.pixel_clock = link_settings->link_rate
cntl              974 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
cntl              976 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	result = link_transmitter_control(enc10, &cntl);
cntl              992 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl             1003 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_ENABLE;
cntl             1004 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl             1005 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.transmitter = enc10->base.transmitter;
cntl             1006 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.pll_id = clock_source;
cntl             1007 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
cntl             1008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.lanes_number = link_settings->lane_count;
cntl             1009 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.hpd_sel = enc10->base.hpd_source;
cntl             1010 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.pixel_clock = link_settings->link_rate
cntl             1013 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
cntl             1015 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	result = link_transmitter_control(enc10, &cntl);
cntl             1032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl             1054 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_DISABLE;
cntl             1055 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.transmitter = enc10->base.transmitter;
cntl             1056 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.hpd_sel = enc10->base.hpd_source;
cntl             1057 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.signal = signal;
cntl             1058 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.connector_obj_id = enc10->base.connector;
cntl             1060 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	result = link_transmitter_control(enc10, &cntl);
cntl             1081 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	struct bp_transmitter_control cntl = { 0 };
cntl             1088 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
cntl             1089 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.transmitter = enc10->base.transmitter;
cntl             1090 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.connector_obj_id = enc10->base.connector;
cntl             1091 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.lanes_number = link_settings->link_settings.lane_count;
cntl             1092 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.hpd_sel = enc10->base.hpd_source;
cntl             1093 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 	cntl.pixel_clock = link_settings->link_settings.link_rate *
cntl             1113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		cntl.lane_select = lane;
cntl             1114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		cntl.lane_settings = training_lane_set.raw;
cntl             1117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c 		link_transmitter_control(enc10, &cntl);
cntl              499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	struct bp_encoder_control cntl = {0};
cntl              501 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.action = ENCODER_CONTROL_SETUP;
cntl              502 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.engine_id = enc1->base.id;
cntl              503 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
cntl              504 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.enable_dp_audio = enable_audio;
cntl              505 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.pixel_clock = actual_pix_clk_khz;
cntl              506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.lanes_number = LANE_COUNT_FOUR;
cntl              509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 			enc1->base.bp, &cntl) != BP_RESULT_OK)
cntl              605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	struct bp_encoder_control cntl = {0};
cntl              607 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.action = ENCODER_CONTROL_SETUP;
cntl              608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.engine_id = enc1->base.id;
cntl              609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.signal = is_dual_link ?
cntl              611 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.enable_dp_audio = false;
cntl              612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
cntl              613 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
cntl              616 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 			enc1->base.bp, &cntl) != BP_RESULT_OK)
cntl             10633 drivers/gpu/drm/i915/display/intel_display.c 	u32 cntl = 0;
cntl             10636 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= CURSOR_GAMMA_ENABLE;
cntl             10638 drivers/gpu/drm/i915/display/intel_display.c 	return cntl;
cntl             10707 drivers/gpu/drm/i915/display/intel_display.c 	u32 cntl = 0, base = 0, pos = 0, size = 0;
cntl             10714 drivers/gpu/drm/i915/display/intel_display.c 		cntl = plane_state->ctl |
cntl             10730 drivers/gpu/drm/i915/display/intel_display.c 	    plane->cursor.cntl != cntl) {
cntl             10735 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
cntl             10739 drivers/gpu/drm/i915/display/intel_display.c 		plane->cursor.cntl = cntl;
cntl             10787 drivers/gpu/drm/i915/display/intel_display.c 	u32 cntl = 0;
cntl             10790 drivers/gpu/drm/i915/display/intel_display.c 		return cntl;
cntl             10793 drivers/gpu/drm/i915/display/intel_display.c 		cntl = MCURSOR_GAMMA_ENABLE;
cntl             10796 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= MCURSOR_PIPE_CSC_ENABLE;
cntl             10799 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
cntl             10801 drivers/gpu/drm/i915/display/intel_display.c 	return cntl;
cntl             10809 drivers/gpu/drm/i915/display/intel_display.c 	u32 cntl = 0;
cntl             10812 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
cntl             10816 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= MCURSOR_MODE_64_ARGB_AX;
cntl             10819 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= MCURSOR_MODE_128_ARGB_AX;
cntl             10822 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= MCURSOR_MODE_256_ARGB_AX;
cntl             10830 drivers/gpu/drm/i915/display/intel_display.c 		cntl |= MCURSOR_ROTATE_180;
cntl             10832 drivers/gpu/drm/i915/display/intel_display.c 	return cntl;
cntl             10934 drivers/gpu/drm/i915/display/intel_display.c 	u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
cntl             10938 drivers/gpu/drm/i915/display/intel_display.c 		cntl = plane_state->ctl |
cntl             10975 drivers/gpu/drm/i915/display/intel_display.c 	    plane->cursor.cntl != cntl) {
cntl             10978 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE_FW(CURCNTR(pipe), cntl);
cntl             10984 drivers/gpu/drm/i915/display/intel_display.c 		plane->cursor.cntl = cntl;
cntl             14980 drivers/gpu/drm/i915/display/intel_display.c 	cursor->cursor.cntl = ~0;
cntl             1042 drivers/gpu/drm/i915/display/intel_display_types.h 		u32 base, cntl, size;
cntl              102 drivers/gpu/drm/msm/adreno/a5xx_gpu.h 	uint32_t cntl;
cntl              250 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT;
cntl              132 drivers/gpu/drm/pl111/pl111_display.c 	u32 cntl;
cntl              243 drivers/gpu/drm/pl111/pl111_display.c 		cntl = CNTL_LCDEN | CNTL_LCDMONO8;
cntl              246 drivers/gpu/drm/pl111/pl111_display.c 		cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
cntl              250 drivers/gpu/drm/pl111/pl111_display.c 		cntl |= CNTL_ST_CDWID_24;
cntl              262 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR;
cntl              267 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_ST_LCDBPP24_PACKED;
cntl              272 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP24 | CNTL_BGR;
cntl              274 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP24;
cntl              279 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP24;
cntl              281 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP24 | CNTL_BGR;
cntl              285 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP16;
cntl              287 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR;
cntl              289 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP16_565;
cntl              293 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP16 | CNTL_BGR;
cntl              295 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565;
cntl              297 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
cntl              301 drivers/gpu/drm/pl111/pl111_display.c 		cntl |= CNTL_LCDBPP16;
cntl              303 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR;
cntl              307 drivers/gpu/drm/pl111/pl111_display.c 		cntl |= CNTL_LCDBPP16;
cntl              309 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_ST_1XBPP_5551;
cntl              311 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_BGR;
cntl              315 drivers/gpu/drm/pl111/pl111_display.c 		cntl |= CNTL_LCDBPP16_444;
cntl              317 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR;
cntl              321 drivers/gpu/drm/pl111/pl111_display.c 		cntl |= CNTL_LCDBPP16_444;
cntl              323 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_ST_1XBPP_444;
cntl              325 drivers/gpu/drm/pl111/pl111_display.c 			cntl |= CNTL_BGR;
cntl              335 drivers/gpu/drm/pl111/pl111_display.c 		cntl &= ~CNTL_BGR;
cntl              338 drivers/gpu/drm/pl111/pl111_display.c 	writel(cntl, priv->regs + priv->ctrl);
cntl              350 drivers/gpu/drm/pl111/pl111_display.c 	cntl |= CNTL_LCDPWR;
cntl              351 drivers/gpu/drm/pl111/pl111_display.c 	writel(cntl, priv->regs + priv->ctrl);
cntl              362 drivers/gpu/drm/pl111/pl111_display.c 	u32 cntl;
cntl              368 drivers/gpu/drm/pl111/pl111_display.c 	cntl = readl(priv->regs + priv->ctrl);
cntl              369 drivers/gpu/drm/pl111/pl111_display.c 	if (cntl & CNTL_LCDPWR) {
cntl              370 drivers/gpu/drm/pl111/pl111_display.c 		cntl &= ~CNTL_LCDPWR;
cntl              371 drivers/gpu/drm/pl111/pl111_display.c 		writel(cntl, priv->regs + priv->ctrl);
cntl              277 drivers/gpu/drm/radeon/kv_dpm.c 			WREG32_SMC(local_cac_reg->cntl, data);
cntl               59 drivers/gpu/drm/radeon/kv_dpm.h 	u32 cntl;
cntl               89 drivers/i2c/busses/i2c-ibm_iic.c 		in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
cntl              162 drivers/i2c/busses/i2c-ibm_iic.c 	out_8(&iic->cntl, 0);
cntl              382 drivers/i2c/busses/i2c-ibm_iic.c 	out_8(&iic->cntl, CNTL_HMT);
cntl              465 drivers/i2c/busses/i2c-ibm_iic.c 	u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
cntl              467 drivers/i2c/busses/i2c-ibm_iic.c 		cntl |= CNTL_RW;
cntl              472 drivers/i2c/busses/i2c-ibm_iic.c 		u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
cntl              474 drivers/i2c/busses/i2c-ibm_iic.c 		if (!(cntl & CNTL_RW))
cntl              486 drivers/i2c/busses/i2c-ibm_iic.c 		out_8(&iic->cntl, cmd);
cntl              505 drivers/i2c/busses/i2c-ibm_iic.c 		if (cntl & CNTL_RW)
cntl              525 drivers/i2c/busses/i2c-ibm_iic.c 	    out_8(&iic->cntl, CNTL_AMD);
cntl              530 drivers/i2c/busses/i2c-ibm_iic.c 	    out_8(&iic->cntl, 0);
cntl               27 drivers/i2c/busses/i2c-ibm_iic.h 	u8 cntl;
cntl              750 drivers/net/ethernet/micrel/ks8851_mll.c 	u16 cntl;
cntl              753 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl = ks_rdreg16(ks, KS_RXCR1);
cntl              754 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl |= RXCR1_RXE ;
cntl              755 drivers/net/ethernet/micrel/ks8851_mll.c 	ks_wrreg16(ks, KS_RXCR1, cntl);
cntl              765 drivers/net/ethernet/micrel/ks8851_mll.c 	u16 cntl;
cntl              768 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl = ks_rdreg16(ks, KS_RXCR1);
cntl              769 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl &= ~RXCR1_RXE ;
cntl              770 drivers/net/ethernet/micrel/ks8851_mll.c 	ks_wrreg16(ks, KS_RXCR1, cntl);
cntl              840 drivers/net/ethernet/micrel/ks8851_mll.c 	u16		cntl;
cntl              843 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl = ks_rdreg16(ks, KS_RXCR1);
cntl              845 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl &= ~RXCR1_FILTER_MASK;
cntl              848 drivers/net/ethernet/micrel/ks8851_mll.c 		cntl |= RXCR1_RXAE | RXCR1_RXINVF;
cntl              851 drivers/net/ethernet/micrel/ks8851_mll.c 		cntl |= RXCR1_RXPAFMA;
cntl              853 drivers/net/ethernet/micrel/ks8851_mll.c 	ks_wrreg16(ks, KS_RXCR1, cntl);
cntl              862 drivers/net/ethernet/micrel/ks8851_mll.c 	u16	cntl;
cntl              866 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl = ks_rdreg16(ks, KS_RXCR1);
cntl              867 drivers/net/ethernet/micrel/ks8851_mll.c 	cntl &= ~RXCR1_FILTER_MASK;
cntl              870 drivers/net/ethernet/micrel/ks8851_mll.c 		cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
cntl              876 drivers/net/ethernet/micrel/ks8851_mll.c 		cntl |= RXCR1_RXPAFMA;
cntl              878 drivers/net/ethernet/micrel/ks8851_mll.c 	ks_wrreg16(ks, KS_RXCR1, cntl);
cntl               65 drivers/net/wireless/ath/ath6kl/common.h 	u8 cntl;
cntl              197 drivers/net/wireless/ath/ath6kl/wmi.c 	llc_hdr->cntl = 0x03;
cntl              258 drivers/scsi/advansys.c 	uchar cntl;
cntl              302 drivers/scsi/advansys.c 	uchar cntl;
cntl              354 drivers/scsi/advansys.c 	uchar cntl;
cntl              604 drivers/scsi/advansys.c 	ushort cntl;
cntl             1748 drivers/scsi/advansys.c 	uchar cntl;		/* Ucode flags and state (ASC_MC_QC_*). */
cntl             2586 drivers/scsi/advansys.c 	       q->cntl, (ulong)le32_to_cpu(q->data_addr));
cntl             2909 drivers/scsi/advansys.c 		   " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
cntl             6206 drivers/scsi/advansys.c 		scsiq->cntl = 0;
cntl             6707 drivers/scsi/advansys.c 	scsiq->cntl = (uchar)_val;
cntl             6889 drivers/scsi/advansys.c 		if ((scsiq->cntl & QC_SG_HEAD) != 0) {
cntl             6957 drivers/scsi/advansys.c 					     cntl & (QC_DATA_IN | QC_DATA_OUT))
cntl             6983 drivers/scsi/advansys.c 			if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
cntl             7001 drivers/scsi/advansys.c 			if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
cntl             7583 drivers/scsi/advansys.c 		asc_scsi_q->q1.cntl |= QC_SG_HEAD;
cntl             7760 drivers/scsi/advansys.c 	scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
cntl             7977 drivers/scsi/advansys.c 		scsiq->q1.cntl |= QC_MSG_OUT;
cntl             7990 drivers/scsi/advansys.c 		    (uchar *)&scsiq->q1.cntl,
cntl             8029 drivers/scsi/advansys.c 		scsiq->q1.cntl |= QC_SG_HEAD;
cntl             8034 drivers/scsi/advansys.c 		scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
cntl             8052 drivers/scsi/advansys.c 				scsi_sg_q.cntl |= QCSG_SG_XFER_END;
cntl             8084 drivers/scsi/advansys.c 		scsiq->q1.cntl &= ~QC_SG_HEAD;
cntl             8195 drivers/scsi/advansys.c 			scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
cntl             8203 drivers/scsi/advansys.c 	if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
cntl             8215 drivers/scsi/advansys.c 			scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
cntl             8223 drivers/scsi/advansys.c 		if (scsiq->q1.cntl & QC_SG_HEAD) {
cntl             8259 drivers/scsi/advansys.c 	if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
cntl             8303 drivers/scsi/advansys.c 		    || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
cntl             8347 drivers/scsi/advansys.c 		    ((scsiq->q1.cntl & QC_URGENT) != 0)) {
cntl             9170 drivers/scsi/advansys.c 			eep_config->cntl = 0xBFFF;
cntl             9192 drivers/scsi/advansys.c 	asc_dvc->dvc_cntl = eep_config->cntl;
cntl             11051 drivers/scsi/advansys.c 		ep->cntl = asc_dvc_varp->dvc_cntl;
cntl               93 drivers/spi/spi-bcm2835aux.c 	u32 cntl[2];
cntl              250 drivers/spi/spi-bcm2835aux.c 		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
cntl              256 drivers/spi/spi-bcm2835aux.c 		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
cntl              270 drivers/spi/spi-bcm2835aux.c 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
cntl              288 drivers/spi/spi-bcm2835aux.c 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
cntl              289 drivers/spi/spi-bcm2835aux.c 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
cntl              314 drivers/spi/spi-bcm2835aux.c 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
cntl              315 drivers/spi/spi-bcm2835aux.c 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
cntl              373 drivers/spi/spi-bcm2835aux.c 	bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
cntl              375 drivers/spi/spi-bcm2835aux.c 	bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
cntl              410 drivers/spi/spi-bcm2835aux.c 	bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
cntl              413 drivers/spi/spi-bcm2835aux.c 	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
cntl              417 drivers/spi/spi-bcm2835aux.c 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
cntl              418 drivers/spi/spi-bcm2835aux.c 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
cntl              420 drivers/spi/spi-bcm2835aux.c 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
cntl              422 drivers/spi/spi-bcm2835aux.c 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
cntl              423 drivers/spi/spi-bcm2835aux.c 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
cntl               96 drivers/video/fbdev/amba-clcd.c static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
cntl              109 drivers/video/fbdev/amba-clcd.c 	cntl |= CNTL_LCDEN;
cntl              110 drivers/video/fbdev/amba-clcd.c 	writel(cntl, fb->regs + fb->off_cntl);
cntl              117 drivers/video/fbdev/amba-clcd.c 	cntl |= CNTL_LCDPWR;
cntl              118 drivers/video/fbdev/amba-clcd.c 	writel(cntl, fb->regs + fb->off_cntl);
cntl              145 drivers/video/fbdev/amba-clcd.c 		caps = fb->panel->cntl & CNTL_BGR ?
cntl              152 drivers/video/fbdev/amba-clcd.c 	if (!(fb->panel->cntl & CNTL_LCDTFT))
cntl              318 drivers/video/fbdev/amba-clcd.c 	fb->clcd_cntl = regs.cntl;
cntl              320 drivers/video/fbdev/amba-clcd.c 	clcdfb_enable(fb, regs.cntl);
cntl              673 drivers/video/fbdev/amba-clcd.c 	fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1);
cntl              748 drivers/video/fbdev/amba-clcd.c 	fb->panel->cntl |= CNTL_BEBO;
cntl               66 drivers/video/fbdev/macfb.c 	unsigned char cntl; /* a guess as to purpose */
cntl              236 drivers/video/fbdev/macfb.c 	nubus_writeb(0xFF, &rbv_cmap_regs->cntl);
cntl               49 include/linux/amba/clcd.h 	u32			cntl;
cntl               69 include/linux/amba/clcd.h 	u32			cntl;
cntl              158 include/linux/amba/clcd.h 	if (fb->panel->cntl & CNTL_LCDDUAL)
cntl              171 include/linux/amba/clcd.h 	if (fb->panel->cntl & CNTL_LCDTFT)	  /* TFT */
cntl              175 include/linux/amba/clcd.h 	else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
cntl              184 include/linux/amba/clcd.h 	val = fb->panel->cntl;
cntl              238 include/linux/amba/clcd.h 	regs->cntl = val;