cnspci             54 arch/arm/mach-cns3xxx/pcie.c 	struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
cnspci             60 arch/arm/mach-cns3xxx/pcie.c 	if (!cnspci->linked && busno > 0)
cnspci             71 arch/arm/mach-cns3xxx/pcie.c 			base = cnspci->host_regs;
cnspci             77 arch/arm/mach-cns3xxx/pcie.c 			base = cnspci->cfg0_regs;
cnspci             81 arch/arm/mach-cns3xxx/pcie.c 		base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
cnspci            109 arch/arm/mach-cns3xxx/pcie.c 	struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
cnspci            110 arch/arm/mach-cns3xxx/pcie.c 	struct resource *res_io = &cnspci->res_io;
cnspci            111 arch/arm/mach-cns3xxx/pcie.c 	struct resource *res_mem = &cnspci->res_mem;
cnspci            130 arch/arm/mach-cns3xxx/pcie.c 	struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
cnspci            131 arch/arm/mach-cns3xxx/pcie.c 	int irq = cnspci->irqs[!!dev->bus->number];
cnspci            181 arch/arm/mach-cns3xxx/pcie.c static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
cnspci            183 arch/arm/mach-cns3xxx/pcie.c 	int port = cnspci->port;
cnspci            203 arch/arm/mach-cns3xxx/pcie.c 			cnspci->linked = 1;
cnspci            212 arch/arm/mach-cns3xxx/pcie.c static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
cnspci            215 arch/arm/mach-cns3xxx/pcie.c 	void __iomem *base = cnspci->host_regs + (where & 0xffc);
cnspci            229 arch/arm/mach-cns3xxx/pcie.c static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
cnspci            231 arch/arm/mach-cns3xxx/pcie.c 	u16 mem_base  = cnspci->res_mem.start >> 16;
cnspci            232 arch/arm/mach-cns3xxx/pcie.c 	u16 mem_limit = cnspci->res_mem.end   >> 16;
cnspci            233 arch/arm/mach-cns3xxx/pcie.c 	u16 io_base   = cnspci->res_io.start  >> 16;
cnspci            234 arch/arm/mach-cns3xxx/pcie.c 	u16 io_limit  = cnspci->res_io.end    >> 16;
cnspci            236 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
cnspci            237 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
cnspci            238 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
cnspci            239 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
cnspci            240 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
cnspci            241 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
cnspci            242 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);
cnspci            244 arch/arm/mach-cns3xxx/pcie.c 	if (!cnspci->linked)
cnspci            251 arch/arm/mach-cns3xxx/pcie.c 	__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));