cns3xxx_tmr1 111 arch/arm/mach-cns3xxx/core.c static void __iomem *cns3xxx_tmr1; cns3xxx_tmr1 115 arch/arm/mach-cns3xxx/core.c writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 121 arch/arm/mach-cns3xxx/core.c unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 125 arch/arm/mach-cns3xxx/core.c writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 131 arch/arm/mach-cns3xxx/core.c unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 136 arch/arm/mach-cns3xxx/core.c writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); cns3xxx_tmr1 138 arch/arm/mach-cns3xxx/core.c writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 145 arch/arm/mach-cns3xxx/core.c unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 147 arch/arm/mach-cns3xxx/core.c writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); cns3xxx_tmr1 148 arch/arm/mach-cns3xxx/core.c writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 180 arch/arm/mach-cns3xxx/core.c u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET; cns3xxx_tmr1 211 arch/arm/mach-cns3xxx/core.c writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 213 arch/arm/mach-cns3xxx/core.c writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); cns3xxx_tmr1 216 arch/arm/mach-cns3xxx/core.c writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); cns3xxx_tmr1 217 arch/arm/mach-cns3xxx/core.c writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); cns3xxx_tmr1 219 arch/arm/mach-cns3xxx/core.c writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); cns3xxx_tmr1 220 arch/arm/mach-cns3xxx/core.c writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); cns3xxx_tmr1 223 arch/arm/mach-cns3xxx/core.c irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); cns3xxx_tmr1 226 arch/arm/mach-cns3xxx/core.c writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); cns3xxx_tmr1 229 arch/arm/mach-cns3xxx/core.c val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 231 arch/arm/mach-cns3xxx/core.c writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 234 arch/arm/mach-cns3xxx/core.c writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); cns3xxx_tmr1 235 arch/arm/mach-cns3xxx/core.c writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); cns3xxx_tmr1 238 arch/arm/mach-cns3xxx/core.c irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); cns3xxx_tmr1 240 arch/arm/mach-cns3xxx/core.c writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); cns3xxx_tmr1 243 arch/arm/mach-cns3xxx/core.c val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 245 arch/arm/mach-cns3xxx/core.c writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_tmr1 255 arch/arm/mach-cns3xxx/core.c cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);