cmxsi1cr_l 856 drivers/net/wan/fsl_ucc_hdlc.c priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l); cmxsi1cr_l 872 drivers/net/wan/fsl_ucc_hdlc.c iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l); cmxsi1cr_l 112 drivers/net/wan/fsl_ucc_hdlc.h u32 cmxsi1cr_l, cmxsi1cr_h; cmxsi1cr_l 540 drivers/soc/fsl/qe/ucc.c cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l : cmxsi1cr_l 94 include/soc/fsl/qe/immap_qe.h __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */