cmxsi1cr_h        855 drivers/net/wan/fsl_ucc_hdlc.c 	priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
cmxsi1cr_h        871 drivers/net/wan/fsl_ucc_hdlc.c 	iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
cmxsi1cr_h        112 drivers/net/wan/fsl_ucc_hdlc.h 	u32 cmxsi1cr_l, cmxsi1cr_h;
cmxsi1cr_h        541 drivers/soc/fsl/qe/ucc.c 				  &qe_mux_reg->cmxsi1cr_h;
cmxsi1cr_h         95 include/soc/fsl/qe/immap_qe.h 	__be32	cmxsi1cr_h;	/* CMX SI1 clock route high register */