cmn_clk_cfg1      538 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	u32 cmn_clk_cfg0, cmn_clk_cfg1;
cmn_clk_cfg1      548 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
cmn_clk_cfg1      549 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	cached->pll_mux = cmn_clk_cfg1 & 0x3;
cmn_clk_cfg1      104 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	u32 cmn_clk_cfg1;