cmn_base 491 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; cmn_base 496 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); cmn_base 499 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); cmn_base 502 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); cmn_base 511 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *cmn_base = pll->phy_cmn_mmio; cmn_base 517 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); cmn_base 524 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data); cmn_base 527 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); cmn_base 766 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; cmn_base 772 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); cmn_base 788 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; cmn_base 792 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); cmn_base 799 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; cmn_base 802 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); cmn_base 817 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *cmn_base = pll_14nm->phy_cmn_mmio; cmn_base 834 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);