cmd_tables 786 drivers/gpu/drm/i915/i915_cmd_parser.c const struct drm_i915_cmd_table *cmd_tables, cmd_tables 792 drivers/gpu/drm/i915/i915_cmd_parser.c if (!cmd_tables || cmd_table_count == 0) cmd_tables 796 drivers/gpu/drm/i915/i915_cmd_parser.c const struct drm_i915_cmd_table *table = &cmd_tables[i]; cmd_tables 888 drivers/gpu/drm/i915/i915_cmd_parser.c const struct drm_i915_cmd_table *cmd_tables, cmd_tables 896 drivers/gpu/drm/i915/i915_cmd_parser.c const struct drm_i915_cmd_table *table = &cmd_tables[i]; cmd_tables 938 drivers/gpu/drm/i915/i915_cmd_parser.c const struct drm_i915_cmd_table *cmd_tables; cmd_tables 949 drivers/gpu/drm/i915/i915_cmd_parser.c cmd_tables = hsw_render_ring_cmd_table; cmd_tables 953 drivers/gpu/drm/i915/i915_cmd_parser.c cmd_tables = gen7_render_cmd_table; cmd_tables 967 drivers/gpu/drm/i915/i915_cmd_parser.c cmd_tables = gen7_video_cmd_table; cmd_tables 974 drivers/gpu/drm/i915/i915_cmd_parser.c cmd_tables = gen9_blt_cmd_table; cmd_tables 982 drivers/gpu/drm/i915/i915_cmd_parser.c cmd_tables = hsw_blt_ring_cmd_table; cmd_tables 985 drivers/gpu/drm/i915/i915_cmd_parser.c cmd_tables = gen7_blt_cmd_table; cmd_tables 1002 drivers/gpu/drm/i915/i915_cmd_parser.c cmd_tables = hsw_vebox_cmd_table; cmd_tables 1012 drivers/gpu/drm/i915/i915_cmd_parser.c if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) { cmd_tables 1022 drivers/gpu/drm/i915/i915_cmd_parser.c ret = init_hash_table(engine, cmd_tables, cmd_table_count);