cmd_enc            56 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc            70 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	intf_cfg.stream_sel = cmd_enc->stream_sel;
cmd_enc           107 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc;
cmd_enc           113 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
cmd_enc           119 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	atomic_add_unless(&cmd_enc->pending_vblank_cnt, -1, 0);
cmd_enc           120 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	wake_up_all(&cmd_enc->pending_vblank_wq);
cmd_enc           127 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc;
cmd_enc           133 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
cmd_enc           181 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           189 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
cmd_enc           198 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           206 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc->pp_timeout_report_cnt++;
cmd_enc           207 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) {
cmd_enc           210 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	} else if (cmd_enc->pp_timeout_report_cnt == 1) {
cmd_enc           216 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		     cmd_enc->pp_timeout_report_cnt,
cmd_enc           226 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			  cmd_enc->pp_timeout_report_cnt,
cmd_enc           247 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           266 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		cmd_enc->pp_timeout_report_cnt = 0;
cmd_enc           319 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc;
cmd_enc           324 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
cmd_enc           352 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           367 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
cmd_enc           371 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
cmd_enc           393 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		DPU_DEBUG_CMDENC(cmd_enc, "invalid - vsync_hz %u\n",
cmd_enc           416 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc,
cmd_enc           420 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc,
cmd_enc           424 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc,
cmd_enc           428 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc,
cmd_enc           440 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           449 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "pp %d, enabling mode:\n",
cmd_enc           492 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           500 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
cmd_enc           548 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           560 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		DPU_ERROR_CMDENC(cmd_enc, "already disabled\n");
cmd_enc           571 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           578 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	kfree(cmd_enc);
cmd_enc           591 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           616 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n",
cmd_enc           624 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc =
cmd_enc           641 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		DPU_ERROR_CMDENC(cmd_enc, "ctl start interrupt wait failed\n");
cmd_enc           653 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc;
cmd_enc           658 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
cmd_enc           674 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc;
cmd_enc           679 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
cmd_enc           686 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!rc && cmd_enc->serialize_wait4pp)
cmd_enc           696 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc;
cmd_enc           702 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
cmd_enc           708 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	wait_info.wq = &cmd_enc->pending_vblank_wq;
cmd_enc           709 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt;
cmd_enc           712 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	atomic_inc(&cmd_enc->pending_vblank_cnt);
cmd_enc           767 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_encoder_phys_cmd *cmd_enc = NULL;
cmd_enc           773 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);
cmd_enc           774 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!cmd_enc) {
cmd_enc           779 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	phys_enc = &cmd_enc->base;
cmd_enc           790 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	cmd_enc->stream_sel = 0;
cmd_enc           827 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	atomic_set(&cmd_enc->pending_vblank_cnt, 0);
cmd_enc           829 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	init_waitqueue_head(&cmd_enc->pending_vblank_wq);
cmd_enc           831 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "created\n");