ChlWidth 29 drivers/staging/rtl8192e/rtl819x_HT.h u8 ChlWidth:1; ChlWidth 301 drivers/staging/rtl8192e/rtl819x_HTProc.c pCapELE->ChlWidth = 0; ChlWidth 303 drivers/staging/rtl8192e/rtl819x_HTProc.c pCapELE->ChlWidth = (pHT->bRegBW40MHz ? 1 : 0); ChlWidth 321 drivers/staging/rtl8192e/rtl819x_HTProc.c pCapELE->ChlWidth, pCapELE->MaxAMSDUSize, pCapELE->DssCCk); ChlWidth 351 drivers/staging/rtl8192e/rtl819x_HTProc.c pCapELE->ChlWidth = 0; ChlWidth 551 drivers/staging/rtl8192e/rtl819x_HTProc.c HTSetConnectBwMode(ieee, (enum ht_channel_width)(pPeerHTCap->ChlWidth), ChlWidth 2035 drivers/staging/rtl8192e/rtllib_rx.c (ht->bdHTCapBuf))->ChlWidth); ChlWidth 149 drivers/staging/rtl8192e/rtllib_wx.c is40M = (ht_cap->ChlWidth) ? 1 : 0; ChlWidth 150 drivers/staging/rtl8192e/rtllib_wx.c isShortGI = (ht_cap->ChlWidth) ? ChlWidth 141 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c is40M = (ht_cap->ChlWidth) ? 1 : 0; ChlWidth 142 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c isShortGI = (ht_cap->ChlWidth) ? ChlWidth 43 drivers/staging/rtl8192u/ieee80211/rtl819x_HT.h u8 ChlWidth:1; ChlWidth 141 drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c IEEE80211_DEBUG(IEEE80211_DL_HT, "\tSupported Channel Width = %s\n", (pCapELE->ChlWidth) ? "20MHz" : "20/40MHz"); ChlWidth 494 drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c pCapELE->ChlWidth = 0; ChlWidth 496 drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c pCapELE->ChlWidth = (pHT->bRegBW40MHz ? 1 : 0); ChlWidth 517 drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c IEEE80211_DEBUG(IEEE80211_DL_HT, "TX HT cap/info ele BW=%d MaxAMSDUSize:%d DssCCk:%d\n", pCapELE->ChlWidth, pCapELE->MaxAMSDUSize, pCapELE->DssCCk); ChlWidth 877 drivers/staging/rtl8192u/ieee80211/rtl819x_HTProc.c HTSetConnectBwMode(ieee, (enum ht_channel_width)(pPeerHTCap->ChlWidth), (enum ht_extension_chan_offset)(pPeerHTInfo->ExtChlOffset));