clr 75 arch/arm/mach-rpc/irq.c unsigned int irq, clr, set; clr 86 arch/arm/mach-rpc/irq.c clr = IRQ_NOREQUEST; clr 90 arch/arm/mach-rpc/irq.c clr |= IRQ_NOPROBE; clr 100 arch/arm/mach-rpc/irq.c irq_modify_status(irq, clr, set); clr 108 arch/arm/mach-rpc/irq.c irq_modify_status(irq, clr, set); clr 116 arch/arm/mach-rpc/irq.c irq_modify_status(irq, clr, set); clr 123 arch/arm/mach-rpc/irq.c irq_modify_status(irq, clr, set); clr 14 arch/arm/mach-s3c24xx/include/mach/hardware.h extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); clr 583 arch/arm64/include/asm/kvm_host.h void kvm_clr_pmu_events(u32 clr); clr 589 arch/arm64/include/asm/kvm_host.h static inline void kvm_clr_pmu_events(u32 clr) {} clr 48 arch/arm64/kvm/pmu.c void kvm_clr_pmu_events(u32 clr) clr 52 arch/arm64/kvm/pmu.c ctx->pmu_events.events_host &= ~clr; clr 53 arch/arm64/kvm/pmu.c ctx->pmu_events.events_guest &= ~clr; clr 397 arch/microblaze/include/asm/pgtable.h static inline unsigned long pte_update(pte_t *p, unsigned long clr, clr 409 arch/microblaze/include/asm/pgtable.h : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set) clr 513 arch/mips/alchemy/common/irq.c unsigned long clr, clr 521 arch/mips/alchemy/common/irq.c l &= ~clr; clr 73 arch/mips/alchemy/devboards/bcsr.c void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) clr 80 arch/mips/alchemy/devboards/bcsr.c r &= ~clr; clr 256 arch/mips/include/asm/mach-db1x00/bcsr.h void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); clr 45 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg) clr 47 arch/mips/include/asm/mach-ralink/ralink_regs.h u32 val = rt_sysc_r32(reg) & ~clr; clr 296 arch/mips/include/asm/octeon/cvmx-gpio-defs.h uint64_t clr:24; clr 298 arch/mips/include/asm/octeon/cvmx-gpio-defs.h uint64_t clr:24; clr 305 arch/mips/include/asm/octeon/cvmx-gpio-defs.h uint64_t clr:16; clr 307 arch/mips/include/asm/octeon/cvmx-gpio-defs.h uint64_t clr:16; clr 314 arch/mips/include/asm/octeon/cvmx-gpio-defs.h uint64_t clr:20; clr 316 arch/mips/include/asm/octeon/cvmx-gpio-defs.h uint64_t clr:20; clr 193 arch/mips/include/asm/octeon/cvmx-led-defs.h uint64_t clr:32; clr 195 arch/mips/include/asm/octeon/cvmx-led-defs.h uint64_t clr:32; clr 323 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t clr:1; clr 339 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t clr:1; clr 2502 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t clr:1; clr 2518 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t clr:1; clr 3018 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 3020 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 3029 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 3031 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 3040 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 3042 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 3051 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 3053 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t clr:64; clr 307 arch/mips/include/asm/octeon/cvmx-stxx-defs.h uint64_t clr:1; clr 311 arch/mips/include/asm/octeon/cvmx-stxx-defs.h uint64_t clr:1; clr 99 arch/mips/pci/pci-mt7620.c static inline void pcie_m32(u32 clr, u32 set, unsigned reg) clr 103 arch/mips/pci/pci-mt7620.c val &= ~clr; clr 71 arch/mips/pic32/pic32mzda/config.c u32 clr, set; clr 73 arch/mips/pic32/pic32mzda/config.c clr = (0x3ff << 4) | (0x3ff << 16); clr 75 arch/mips/pic32/pic32mzda/config.c return pic32_conf_modify_atomic(PIC32_CFGCON2, clr, set); clr 259 arch/powerpc/include/asm/book3s/32/pgtable.h unsigned long clr, clr 271 arch/powerpc/include/asm/book3s/32/pgtable.h : "r" (p), "r" (clr), "r" (set), "m" (*p) clr 278 arch/powerpc/include/asm/book3s/32/pgtable.h unsigned long clr, clr 292 arch/powerpc/include/asm/book3s/32/pgtable.h : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) clr 148 arch/powerpc/include/asm/book3s/64/hash-4k.h unsigned long clr, unsigned long set); clr 265 arch/powerpc/include/asm/book3s/64/hash-64k.h unsigned long clr, unsigned long set); clr 152 arch/powerpc/include/asm/book3s/64/hash.h pte_t *ptep, unsigned long clr, clr 168 arch/powerpc/include/asm/book3s/64/hash.h : "r" (ptep), "r" (cpu_to_be64(clr)), "m" (*ptep), clr 354 arch/powerpc/include/asm/book3s/64/pgtable.h pte_t *ptep, unsigned long clr, clr 358 arch/powerpc/include/asm/book3s/64/pgtable.h return radix__pte_update(mm, addr, ptep, clr, set, huge); clr 359 arch/powerpc/include/asm/book3s/64/pgtable.h return hash__pte_update(mm, addr, ptep, clr, set, huge); clr 1155 arch/powerpc/include/asm/book3s/64/pgtable.h unsigned long clr, unsigned long set) clr 1158 arch/powerpc/include/asm/book3s/64/pgtable.h return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); clr 1159 arch/powerpc/include/asm/book3s/64/pgtable.h return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); clr 132 arch/powerpc/include/asm/book3s/64/radix.h static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr, clr 144 arch/powerpc/include/asm/book3s/64/radix.h : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr)) clr 152 arch/powerpc/include/asm/book3s/64/radix.h pte_t *ptep, unsigned long clr, clr 158 arch/powerpc/include/asm/book3s/64/radix.h old_pte = __radix_pte_update(ptep, clr, set); clr 248 arch/powerpc/include/asm/book3s/64/radix.h pmd_t *pmdp, unsigned long clr, clr 48 arch/powerpc/include/asm/code-patching.h static inline int modify_instruction(unsigned int *addr, unsigned int clr, clr 51 arch/powerpc/include/asm/code-patching.h return patch_instruction(addr, (*addr & ~clr) | set); clr 54 arch/powerpc/include/asm/code-patching.h static inline int modify_instruction_site(s32 *site, unsigned int clr, unsigned int set) clr 56 arch/powerpc/include/asm/code-patching.h return modify_instruction((unsigned int *)patch_site_addr(site), clr, set); clr 112 arch/powerpc/include/asm/dcr-native.h unsigned clr, unsigned set) clr 120 arch/powerpc/include/asm/dcr-native.h val = (mfdcrx(base_data) & ~clr) | set; clr 124 arch/powerpc/include/asm/dcr-native.h val = (__mfdcr(base_data) & ~clr) | set; clr 138 arch/powerpc/include/asm/dcr-native.h #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ clr 140 arch/powerpc/include/asm/dcr-native.h reg, clr, set) clr 630 arch/powerpc/include/asm/kvm_book3s_64.h unsigned long clr, unsigned long set, clr 222 arch/powerpc/include/asm/nohash/32/pgtable.h unsigned long clr, clr 236 arch/powerpc/include/asm/nohash/32/pgtable.h : "r" (p), "r" (clr), "r" (set), "m" (*p) clr 240 arch/powerpc/include/asm/nohash/32/pgtable.h unsigned long new = (old & ~clr) | set; clr 257 arch/powerpc/include/asm/nohash/32/pgtable.h unsigned long clr, clr 273 arch/powerpc/include/asm/nohash/32/pgtable.h : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) clr 277 arch/powerpc/include/asm/nohash/32/pgtable.h *p = __pte((old & ~(unsigned long long)clr) | set); clr 309 arch/powerpc/include/asm/nohash/32/pgtable.h unsigned long clr = ~pte_val(pte_wrprotect(__pte(~0))); clr 312 arch/powerpc/include/asm/nohash/32/pgtable.h pte_update(ptep, clr, set); clr 323 arch/powerpc/include/asm/nohash/32/pgtable.h unsigned long clr = ~pte_val(entry) & ~pte_val(pte_clr); clr 325 arch/powerpc/include/asm/nohash/32/pgtable.h pte_update(ptep, clr, set); clr 210 arch/powerpc/include/asm/nohash/64/pgtable.h pte_t *ptep, unsigned long clr, clr 224 arch/powerpc/include/asm/nohash/64/pgtable.h : "r" (ptep), "r" (clr), "m" (*ptep), "r" (set) clr 228 arch/powerpc/include/asm/nohash/64/pgtable.h *ptep = __pte((old & ~clr) | set); clr 339 arch/powerpc/kvm/book3s_64_mmu_radix.c unsigned long clr, unsigned long set, clr 342 arch/powerpc/kvm/book3s_64_mmu_radix.c return __radix_pte_update(ptep, clr, set); clr 792 arch/powerpc/kvm/book3s_hv_nested.c unsigned long clr, unsigned long set, clr 815 arch/powerpc/kvm/book3s_hv_nested.c __radix_pte_update(ptep, clr, set); clr 825 arch/powerpc/kvm/book3s_hv_nested.c unsigned long clr, unsigned long set, clr 832 arch/powerpc/kvm/book3s_hv_nested.c if ((clr | set) & ~(_PAGE_DIRTY | _PAGE_ACCESSED)) clr 839 arch/powerpc/kvm/book3s_hv_nested.c kvmhv_update_nest_rmap_rc(kvm, rmap, clr, set, hpa, mask); clr 190 arch/powerpc/mm/book3s64/hash_pgtable.c pmd_t *pmdp, unsigned long clr, clr 210 arch/powerpc/mm/book3s64/hash_pgtable.c : "r" (pmdp), "r" (cpu_to_be64(clr)), "m" (*pmdp), clr 216 arch/powerpc/mm/book3s64/hash_pgtable.c trace_hugepage_update(addr, old, clr, set); clr 924 arch/powerpc/mm/book3s64/radix_pgtable.c pmd_t *pmdp, unsigned long clr, clr 934 arch/powerpc/mm/book3s64/radix_pgtable.c old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1); clr 935 arch/powerpc/mm/book3s64/radix_pgtable.c trace_hugepage_update(addr, old, clr, set); clr 22 arch/sparc/include/asm/asmmacro.h #define RESTORE_ALL b ret_trap_entry; clr %l6; clr 64 arch/sparc/include/asm/backoff.h clr tmp; \ clr 88 arch/sparc/include/asm/ns87303.h unsigned char clr, unsigned char set) clr 106 arch/sparc/include/asm/ns87303.h value &= ~(reserved[index] | clr); clr 18 arch/sparc/include/asm/ttable.h clr %o0; clr %o1; clr %o2; clr %o3; \ clr 19 arch/sparc/include/asm/ttable.h clr %o4; clr %o5; clr %o6; clr %o7; \ clr 20 arch/sparc/include/asm/ttable.h clr %l0; clr %l1; clr %l2; clr %l3; \ clr 21 arch/sparc/include/asm/ttable.h clr %l4; clr %l5; clr %l6; clr %l7; \ clr 598 drivers/ata/pata_octeon_cf.c mio_boot_dma_cfg.s.clr = 0; clr 91 drivers/clocksource/timer-armada-370-xp.c static void local_timer_ctrl_clrset(u32 clr, u32 set) clr 93 drivers/clocksource/timer-armada-370-xp.c writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, clr 176 drivers/clocksource/timer-armada-370-xp.c u32 clr = 0, set = 0; clr 181 drivers/clocksource/timer-armada-370-xp.c clr = TIMER0_25MHZ; clr 182 drivers/clocksource/timer-armada-370-xp.c local_timer_ctrl_clrset(clr, set); clr 245 drivers/clocksource/timer-armada-370-xp.c u32 clr = 0, set = 0; clr 264 drivers/clocksource/timer-armada-370-xp.c clr = TIMER0_25MHZ; clr 267 drivers/clocksource/timer-armada-370-xp.c atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); clr 268 drivers/clocksource/timer-armada-370-xp.c local_timer_ctrl_clrset(clr, set); clr 129 drivers/dma/st_fdma.c unsigned long int_sta, clr; clr 132 drivers/dma/st_fdma.c clr = int_sta; clr 160 drivers/dma/st_fdma.c fdma_write(fdev, clr, FDMA_INT_CLR_OFST); clr 239 drivers/dma/ste_dma40.c u32 clr; clr 1684 drivers/dma/ste_dma40.c writel(BIT(idx), base->virtbase + il[row].clr); clr 489 drivers/dma/xilinx/xilinx_dma.c u32 clr) clr 491 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); clr 477 drivers/gpio/gpio-mmio.c void __iomem *clr, clr 485 drivers/gpio/gpio-mmio.c if (set && clr) { clr 487 drivers/gpio/gpio-mmio.c gc->reg_clr = clr; clr 490 drivers/gpio/gpio-mmio.c } else if (set && !clr) { clr 584 drivers/gpio/gpio-mmio.c void __iomem *clr, void __iomem *dirout, void __iomem *dirin, clr 604 drivers/gpio/gpio-mmio.c ret = bgpio_setup_io(gc, dat, set, clr, flags); clr 713 drivers/gpio/gpio-mmio.c void __iomem *clr; clr 745 drivers/gpio/gpio-mmio.c clr = bgpio_map(pdev, "clr", sz); clr 746 drivers/gpio/gpio-mmio.c if (IS_ERR(clr)) clr 747 drivers/gpio/gpio-mmio.c return PTR_ERR(clr); clr 761 drivers/gpio/gpio-mmio.c err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); clr 37 drivers/gpu/drm/i915/gt/intel_gt.c static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) clr 39 drivers/gpu/drm/i915/gt/intel_gt.c intel_uncore_rmw(uncore, reg, clr, 0); clr 35 drivers/gpu/drm/i915/gt/intel_reset.c static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) clr 37 drivers/gpu/drm/i915/gt/intel_reset.c intel_uncore_rmw_fw(uncore, reg, clr, 0); clr 140 drivers/gpu/drm/nouveau/dispnv50/atom.h } set, clr; clr 244 drivers/gpu/drm/nouveau/dispnv50/atom.h } set, clr; clr 73 drivers/gpu/drm/nouveau/dispnv50/disp.c } set, clr; clr 1853 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->clr.mask, asyh->set.mask); clr 1860 drivers/gpu/drm/nouveau/dispnv50/disp.c if (asyh->clr.mask) { clr 1872 drivers/gpu/drm/nouveau/dispnv50/disp.c asyw->clr.mask, asyw->set.mask); clr 1873 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!asyw->clr.mask) clr 1888 drivers/gpu/drm/nouveau/dispnv50/disp.c outp->clr.mask, outp->set.mask); clr 1890 drivers/gpu/drm/nouveau/dispnv50/disp.c if (outp->clr.mask) { clr 1919 drivers/gpu/drm/nouveau/dispnv50/disp.c outp->set.mask, outp->clr.mask); clr 1936 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->set.mask, asyh->clr.mask); clr 1959 drivers/gpu/drm/nouveau/dispnv50/disp.c asyw->set.mask, asyw->clr.mask); clr 1961 drivers/gpu/drm/nouveau/dispnv50/disp.c (!asyw->clr.mask || atom->flush_disable)) clr 2129 drivers/gpu/drm/nouveau/dispnv50/disp.c outp->clr.ctrl = true; clr 37 drivers/gpu/drm/nouveau/dispnv50/head.c union nv50_head_atom_mask clr = { clr 38 drivers/gpu/drm/nouveau/dispnv50/head.c .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), clr 40 drivers/gpu/drm/nouveau/dispnv50/head.c if (clr.olut) head->func->olut_clr(head); clr 41 drivers/gpu/drm/nouveau/dispnv50/head.c if (clr.core) head->func->core_clr(head); clr 42 drivers/gpu/drm/nouveau/dispnv50/head.c if (clr.curs) head->func->curs_clr(head); clr 371 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.core = true; clr 379 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.curs = true; clr 387 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.olut = true; clr 390 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.olut = armh->olut.visible; clr 391 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.core = armh->core.visible; clr 392 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.curs = armh->curs.visible; clr 398 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->clr.mask || asyh->set.mask) clr 437 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.mask = 0; clr 117 drivers/gpu/drm/nouveau/dispnv50/wndw.c union nv50_wndw_atom_mask clr = { clr 118 drivers/gpu/drm/nouveau/dispnv50/wndw.c .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), clr 120 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (clr.sema ) wndw->func-> sema_clr(wndw); clr 121 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); clr 122 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (clr.xlut ) wndw->func-> xlut_clr(wndw); clr 123 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (clr.csc ) wndw->func-> csc_clr(wndw); clr 124 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (clr.image) wndw->func->image_clr(wndw); clr 367 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.xlut = armw->xlut.handle != 0; clr 382 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.csc = armw->csc.valid; clr 451 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.ntfy = armw->ntfy.handle != 0; clr 452 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.sema = armw->sema.handle != 0; clr 453 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.xlut = armw->xlut.handle != 0; clr 454 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (asyw->clr.xlut && asyw->visible) clr 456 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.csc = armw->csc.valid; clr 458 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.image = armw->image.handle[0] != 0; clr 551 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.mask = 0; clr 49 drivers/gpu/drm/nouveau/nvkm/core/memory.c u32 nr, void (*clr)(struct nvkm_device *, u32, u32), clr 78 drivers/gpu/drm/nouveau/nvkm/core/memory.c if (clr) clr 79 drivers/gpu/drm/nouveau/nvkm/core/memory.c clr(device, tags->mn->offset, tags->mn->length); clr 47 drivers/gpu/drm/rcar-du/rcar_du_crtc.c static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr) clr 52 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); clr 63 drivers/gpu/drm/rcar-du/rcar_du_crtc.c void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set) clr 67 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set; clr 110 drivers/gpu/drm/rcar-du/rcar_du_crtc.h void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set); clr 201 drivers/i2c/busses/i2c-sh_mobile.c unsigned char set, unsigned char clr) clr 203 drivers/i2c/busses/i2c-sh_mobile.c iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); clr 355 drivers/i2c/busses/i2c-xiic.c u32 clr = 0; clr 400 drivers/i2c/busses/i2c-xiic.c clr |= XIIC_INTR_RX_FULL_MASK; clr 414 drivers/i2c/busses/i2c-xiic.c clr |= (isr & XIIC_INTR_TX_ERROR_MASK); clr 436 drivers/i2c/busses/i2c-xiic.c clr |= XIIC_INTR_BNB_MASK; clr 453 drivers/i2c/busses/i2c-xiic.c clr |= (pend & clr 487 drivers/i2c/busses/i2c-xiic.c dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); clr 489 drivers/i2c/busses/i2c-xiic.c xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); clr 259 drivers/iio/dac/ad5360.c unsigned int clr) clr 267 drivers/iio/dac/ad5360.c st->ctrl &= ~clr; clr 183 drivers/iio/dac/ad5421.c unsigned int clr) clr 190 drivers/iio/dac/ad5421.c st->ctrl &= ~clr; clr 229 drivers/iio/dac/ad5755.c unsigned int channel, unsigned int set, unsigned int clr) clr 235 drivers/iio/dac/ad5755.c st->ctrl[channel] &= ~clr; clr 4744 drivers/infiniband/hw/hns/hns_roce_hw_v2.c struct hns_roce_sccc_clr *clr; clr 4760 drivers/infiniband/hw/hns/hns_roce_hw_v2.c clr = (struct hns_roce_sccc_clr *)desc.data; clr 4761 drivers/infiniband/hw/hns/hns_roce_hw_v2.c clr->qpn = cpu_to_le32(hr_qp->qpn); clr 5560 drivers/infiniband/hw/qib/qib_iba7322.c u64 clr; clr 5565 drivers/infiniband/hw/qib/qib_iba7322.c clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) & clr 5568 drivers/infiniband/hw/qib/qib_iba7322.c if (clr) clr 5569 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_ibcstatus_b, clr); clr 5595 drivers/infiniband/hw/qib/qib_iba7322.c clr = read_7322_creg32_port(ppd, crp_iblinkdown); clr 5596 drivers/infiniband/hw/qib/qib_iba7322.c if (clr == ppd->cpspec->iblnkdownsnap) clr 2979 drivers/iommu/arm-smmu-v3.c static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) clr 2989 drivers/iommu/arm-smmu-v3.c reg &= ~clr; clr 220 drivers/irqchip/irq-bcm7120-l2.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 271 drivers/irqchip/irq-bcm7120-l2.c dn->full_name, handle_level_irq, clr, 0, flags); clr 163 drivers/irqchip/irq-brcmstb-l2.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 213 drivers/irqchip/irq-brcmstb-l2.c np->full_name, init_params->handler, clr, 0, flags); clr 75 drivers/irqchip/irq-digicolor.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 106 drivers/irqchip/irq-digicolor.c clr, 0, 0); clr 71 drivers/irqchip/irq-dw-apb-ictl.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 132 drivers/irqchip/irq-dw-apb-ictl.c handle_level_irq, clr, 0, clr 1055 drivers/irqchip/irq-gic-v3-its.c static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) clr 1071 drivers/irqchip/irq-gic-v3-its.c map->properties &= ~clr; clr 1079 drivers/irqchip/irq-gic-v3-its.c *cfg &= ~clr; clr 1093 drivers/irqchip/irq-gic-v3-its.c static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) clr 1097 drivers/irqchip/irq-gic-v3-its.c lpi_write_config(d, clr, set); clr 86 drivers/irqchip/irq-nvic.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 113 drivers/irqchip/irq-nvic.c clr, 0, IRQ_GC_INIT_MASK_CACHE); clr 55 drivers/irqchip/irq-orion.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 71 drivers/irqchip/irq-orion.c handle_level_irq, clr, 0, clr 141 drivers/irqchip/irq-orion.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 158 drivers/irqchip/irq-orion.c handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); clr 217 drivers/irqchip/irq-pic32-evic.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 251 drivers/irqchip/irq-pic32-evic.c clr, 0, 0); clr 38 drivers/irqchip/irq-sirfsoc.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 45 drivers/irqchip/irq-sirfsoc.c handle_level_irq, clr, set, clr 718 drivers/irqchip/irq-stm32-exti.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 737 drivers/irqchip/irq-stm32-exti.c handle_edge_irq, clr, 0, 0); clr 165 drivers/irqchip/irq-sunxi-nmi.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 176 drivers/irqchip/irq-sunxi-nmi.c handle_fasteoi_irq, clr, 0, clr 72 drivers/irqchip/irq-zevio.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 101 drivers/irqchip/irq-zevio.c clr, 0, IRQ_GC_INIT_MASK_CACHE); clr 516 drivers/leds/leds-bd2802.c #define BD2802_CONTROL_RGBS(name, id, clr) \ clr 523 drivers/leds/leds-bd2802.c led->color = clr; \ clr 541 drivers/leds/leds-bd2802.c led->color = clr; \ clr 85 drivers/mailbox/imx-mailbox.c static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) clr 92 drivers/mailbox/imx-mailbox.c val &= ~clr; clr 927 drivers/media/i2c/tc358743.c unsigned int clr = 0; clr 933 drivers/media/i2c/tc358743.c clr |= MASK_CECRICLR; clr 935 drivers/media/i2c/tc358743.c clr |= MASK_CECTICLR; clr 936 drivers/media/i2c/tc358743.c i2c_wr32(sd, CECICLR, clr); clr 678 drivers/media/pci/intel/ipu3/ipu3-cio2.c u32 clr = 0; clr 683 drivers/media/pci/intel/ipu3/ipu3-cio2.c clr |= CIO2_INT_IOC(d); clr 686 drivers/media/pci/intel/ipu3/ipu3-cio2.c int_status &= ~clr; clr 691 drivers/media/pci/intel/ipu3/ipu3-cio2.c u32 clr = 0; clr 696 drivers/media/pci/intel/ipu3/ipu3-cio2.c clr |= CIO2_INT_IOS_IOLN(d); clr 701 drivers/media/pci/intel/ipu3/ipu3-cio2.c int_status &= ~clr; clr 194 drivers/media/platform/xilinx/xilinx-vip.c void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set) clr 199 drivers/media/platform/xilinx/xilinx-vip.c reg &= ~clr; clr 144 drivers/media/platform/xilinx/xilinx-vip.h static inline void xvip_clr(struct xvip_device *xvip, u32 addr, u32 clr) clr 146 drivers/media/platform/xilinx/xilinx-vip.h xvip_write(xvip, addr, xvip_read(xvip, addr) & ~clr); clr 155 drivers/media/platform/xilinx/xilinx-vip.h void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set); clr 402 drivers/misc/hpilo.c static inline void clear_pending_db(struct ilo_hwinfo *hw, int clr) clr 404 drivers/misc/hpilo.c iowrite32(clr, &hw->mmio_vaddr[DB_OUT]); clr 245 drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) clr 250 drivers/mtd/spi-nor/cadence-quadspi.c (((clr ? ~val : val) & mask) == mask), clr 736 drivers/net/can/c_can/c_can.c u32 idx, obj, pkts = 0, bytes = 0, pend, clr; clr 738 drivers/net/can/c_can/c_can.c clr = pend = priv->read_reg(priv, C_CAN_INTPND2_REG); clr 751 drivers/net/can/c_can/c_can.c atomic_sub(clr, &priv->tx_active); clr 753 drivers/net/can/c_can/c_can.c if (clr & (1 << (C_CAN_MSG_OBJ_TX_NUM - 1))) clr 6799 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) clr 6812 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (clr) clr 6819 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (clr) clr 4647 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); clr 9396 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); clr 10236 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); clr 10265 drivers/net/ethernet/mellanox/mlxsw/reg.h enum mlxsw_reg_sbxx_dir dir, bool clr, clr 10272 drivers/net/ethernet/mellanox/mlxsw/reg.h mlxsw_reg_sbpm_clr_set(payload, clr); clr 10360 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); clr 10400 drivers/net/ethernet/mellanox/mlxsw/reg.h static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) clr 10403 drivers/net/ethernet/mellanox/mlxsw/reg.h mlxsw_reg_sbsr_clr_set(payload, clr); clr 718 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c bool clr) clr 727 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c mlxsw_reg_mogcr_ptp_iftc_set(mogcr_pl, clr); clr 728 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c mlxsw_reg_mogcr_ptp_eftc_set(mogcr_pl, clr); clr 445 drivers/net/ethernet/qlogic/qlcnic/qlcnic.h u8 clr; /* flag to indicate if dump is cleared */ clr 1673 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (fw_dump->clr) clr 1702 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (!fw_dump->clr) { clr 1722 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c fw_dump->clr = 0; clr 1770 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c if (fw_dump->clr) { clr 1314 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c if (fw_dump->clr) { clr 1390 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c fw_dump->clr = 1; clr 131 drivers/net/wireless/ath/ath.h u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr); clr 127 drivers/net/wireless/ath/ath9k/ar9003_wow.c u32 set, clr; clr 160 drivers/net/wireless/ath/ath9k/ar9003_wow.c clr = AR_WOW_LENGTH1_MASK(pattern_count); clr 161 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_RMW(ah, AR_WOW_LENGTH1, set, clr); clr 165 drivers/net/wireless/ath/ath9k/ar9003_wow.c clr = AR_WOW_LENGTH2_MASK(pattern_count); clr 166 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_RMW(ah, AR_WOW_LENGTH2, set, clr); clr 170 drivers/net/wireless/ath/ath9k/ar9003_wow.c clr = AR_WOW_LENGTH3_MASK(pattern_count); clr 171 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_RMW(ah, AR_WOW_LENGTH3, set, clr); clr 175 drivers/net/wireless/ath/ath9k/ar9003_wow.c clr = AR_WOW_LENGTH4_MASK(pattern_count); clr 176 drivers/net/wireless/ath/ath9k/ar9003_wow.c REG_RMW(ah, AR_WOW_LENGTH4, set, clr); clr 1010 drivers/net/wireless/ath/ath9k/eeprom_4k.c u32 pwrctrl, mask, clr; clr 1014 drivers/net/wireless/ath/ath9k/eeprom_4k.c clr = mask * 0x1f; clr 1016 drivers/net/wireless/ath/ath9k/eeprom_4k.c REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); clr 1017 drivers/net/wireless/ath/ath9k/eeprom_4k.c REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); clr 1018 drivers/net/wireless/ath/ath9k/eeprom_4k.c REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); clr 1022 drivers/net/wireless/ath/ath9k/eeprom_4k.c clr = mask * 0x1f; clr 1023 drivers/net/wireless/ath/ath9k/eeprom_4k.c REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); clr 1027 drivers/net/wireless/ath/ath9k/eeprom_4k.c clr = mask * 0x1f; clr 1028 drivers/net/wireless/ath/ath9k/eeprom_4k.c REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); clr 1029 drivers/net/wireless/ath/ath9k/eeprom_4k.c REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); clr 384 drivers/net/wireless/ath/ath9k/htc_drv_init.c u32 reg_offset, u32 set, u32 clr) clr 399 drivers/net/wireless/ath/ath9k/htc_drv_init.c priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].clr = clr 400 drivers/net/wireless/ath/ath9k/htc_drv_init.c cpu_to_be32(clr); clr 467 drivers/net/wireless/ath/ath9k/htc_drv_init.c u32 reg_offset, u32 set, u32 clr) clr 477 drivers/net/wireless/ath/ath9k/htc_drv_init.c buf.clr = cpu_to_be32(clr); clr 489 drivers/net/wireless/ath/ath9k/htc_drv_init.c static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) clr 499 drivers/net/wireless/ath/ath9k/htc_drv_init.c val &= ~clr; clr 507 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_reg_rmw_buffer(hw_priv, reg_offset, set, clr); clr 509 drivers/net/wireless/ath/ath9k/htc_drv_init.c ath9k_reg_rmw_single(hw_priv, reg_offset, set, clr); clr 216 drivers/net/wireless/ath/ath9k/init.c u32 set, u32 clr) clr 221 drivers/net/wireless/ath/ath9k/init.c val &= ~clr; clr 228 drivers/net/wireless/ath/ath9k/init.c static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) clr 238 drivers/net/wireless/ath/ath9k/init.c val = __ath9k_reg_rmw(sc, reg_offset, set, clr); clr 241 drivers/net/wireless/ath/ath9k/init.c val = __ath9k_reg_rmw(sc, reg_offset, set, clr); clr 139 drivers/net/wireless/ath/ath9k/wmi.h __be32 clr; clr 158 drivers/phy/allwinner/phy-sun4i-usb.c static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set) clr 165 drivers/phy/allwinner/phy-sun4i-usb.c iscr &= ~clr; clr 3028 drivers/pinctrl/pinctrl-rockchip.c unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; clr 3058 drivers/pinctrl/pinctrl-rockchip.c clr, 0, IRQ_GC_INIT_MASK_CACHE); clr 200 drivers/spi/spi-lantiq-ssc.c static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, clr 205 drivers/spi/spi-lantiq-ssc.c val &= ~clr; clr 160 drivers/spi/spi-pic32-sqi.c static inline void pic32_clrbits(void __iomem *reg, u32 clr) clr 162 drivers/spi/spi-pic32-sqi.c writel(readl(reg) & ~clr, reg); clr 898 drivers/spi/spi-s3c64xx.c unsigned int val, clr = 0; clr 903 drivers/spi/spi-s3c64xx.c clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; clr 907 drivers/spi/spi-s3c64xx.c clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; clr 911 drivers/spi/spi-s3c64xx.c clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; clr 915 drivers/spi/spi-s3c64xx.c clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; clr 920 drivers/spi/spi-s3c64xx.c writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); clr 221 drivers/spi/spi-sh-msiof.c u32 clr, u32 set) clr 223 drivers/spi/spi-sh-msiof.c u32 mask = clr | set; clr 227 drivers/spi/spi-sh-msiof.c data &= ~clr; clr 554 drivers/spi/spi-sh-msiof.c u32 clr, set, tmp; clr 564 drivers/spi/spi-sh-msiof.c clr = MDR1_SYNCMD_MASK; clr 567 drivers/spi/spi-sh-msiof.c clr |= BIT(MDR1_SYNCAC_SHIFT); clr 571 drivers/spi/spi-sh-msiof.c tmp = sh_msiof_read(p, TMDR1) & ~clr; clr 573 drivers/spi/spi-sh-msiof.c tmp = sh_msiof_read(p, RMDR1) & ~clr; clr 236 drivers/spi/spi-topcliff-pch.c u32 set, u32 clr) clr 239 drivers/spi/spi-topcliff-pch.c tmp = (tmp & ~clr) | set; clr 194 drivers/staging/media/omap4iss/iss.h u32 offset, u32 clr) clr 198 drivers/staging/media/omap4iss/iss.h iss_reg_write(iss, res, offset, v & ~clr); clr 229 drivers/staging/media/omap4iss/iss.h u32 offset, u32 clr, u32 set) clr 233 drivers/staging/media/omap4iss/iss.h iss_reg_write(iss, res, offset, (v & ~clr) | set); clr 39 drivers/staging/sm750fb/sm750_accel.c u32 reg, clr; clr 46 drivers/staging/sm750fb/sm750_accel.c clr = DE_STRETCH_FORMAT_PATTERN_XY | clr 54 drivers/staging/sm750fb/sm750_accel.c (read_dpr(accel, DE_STRETCH_FORMAT) & ~clr) | reg); clr 63 drivers/staging/sm750fb/sm750_accel.c clr = DE_CONTROL_TRANSPARENCY | DE_CONTROL_TRANSPARENCY_MATCH | clr 67 drivers/staging/sm750fb/sm750_accel.c write_dpr(accel, DE_CONTROL, read_dpr(accel, DE_CONTROL) & ~clr); clr 261 drivers/tty/serial/sb1250-duart.c unsigned int clr = 0, set = 0, mode2; clr 266 drivers/tty/serial/sb1250-duart.c clr |= M_DUART_CLR_OPR2; clr 270 drivers/tty/serial/sb1250-duart.c clr |= M_DUART_CLR_OPR0; clr 271 drivers/tty/serial/sb1250-duart.c clr <<= (uport->line) % 2; clr 281 drivers/tty/serial/sb1250-duart.c write_sbdshr(sport, R_DUART_CLEAR_OPR, clr); clr 534 drivers/usb/gadget/udc/aspeed-vhub/hub.c u16 set, clr, speed; clr 560 drivers/usb/gadget/udc/aspeed-vhub/hub.c clr = USB_PORT_STAT_HIGH_SPEED; clr 564 drivers/usb/gadget/udc/aspeed-vhub/hub.c clr = USB_PORT_STAT_LOW_SPEED | clr 569 drivers/usb/gadget/udc/aspeed-vhub/hub.c clr = USB_PORT_STAT_LOW_SPEED; clr 577 drivers/usb/gadget/udc/aspeed-vhub/hub.c clr |= USB_PORT_STAT_RESET; clr 581 drivers/usb/gadget/udc/aspeed-vhub/hub.c ast_vhub_change_port_stat(vhub, port, clr, set, true); clr 531 drivers/usb/phy/phy-isp1301-omap.c u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP; clr 552 drivers/usb/phy/phy-isp1301-omap.c clr |= OTG1_DP_PULLDOWN; clr 563 drivers/usb/phy/phy-isp1301-omap.c clr |= OTG1_DP_PULLUP; clr 569 drivers/usb/phy/phy-isp1301-omap.c else clr |= ISP; \ clr 591 drivers/usb/phy/phy-isp1301-omap.c clr |= OTG1_VBUS_DRV; clr 609 drivers/usb/phy/phy-isp1301-omap.c isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, clr); clr 617 drivers/usb/phy/phy-isp1301-omap.c if (clr & OTG1_DP_PULLUP) clr 623 drivers/usb/phy/phy-isp1301-omap.c if (clr & OTG1_DP_PULLUP) clr 429 drivers/usb/serial/ark3116.c unsigned set, unsigned clr) clr 448 drivers/usb/serial/ark3116.c if (clr & TIOCM_RTS) clr 450 drivers/usb/serial/ark3116.c if (clr & TIOCM_DTR) clr 452 drivers/usb/serial/ark3116.c if (clr & TIOCM_OUT1) clr 454 drivers/usb/serial/ark3116.c if (clr & TIOCM_OUT2) clr 153 drivers/video/fbdev/hpfb.c u8 clr; clr 155 drivers/video/fbdev/hpfb.c clr = region->color & 0xff; clr 161 drivers/video/fbdev/hpfb.c out_8(fb_regs + TC_WEN, fb_bitmask & clr); clr 165 drivers/video/fbdev/hpfb.c out_8(fb_regs + TC_WEN, fb_bitmask & ~clr); clr 621 drivers/video/fbdev/matrox/matroxfb_base.c #define SETCLR(clr)\ clr 622 drivers/video/fbdev/matrox/matroxfb_base.c var->clr.offset = rgbt->clr.offset;\ clr 623 drivers/video/fbdev/matrox/matroxfb_base.c var->clr.length = rgbt->clr.length clr 561 include/linux/gpio/driver.h void __iomem *clr, void __iomem *dirout, void __iomem *dirin, clr 710 include/linux/irq.h void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); clr 717 include/linux/irq.h static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) clr 719 include/linux/irq.h irq_modify_status(irq, clr, 0); clr 1085 include/linux/irq.h enum irq_gc_flags flags, unsigned int clr, clr 1089 include/linux/irq.h unsigned int clr, unsigned int set); clr 1097 include/linux/irq.h unsigned int clr, unsigned int set); clr 1104 include/linux/irq.h unsigned int clr, unsigned int set, clr 1108 include/linux/irq.h handler, clr, set, flags) \ clr 1112 include/linux/irq.h handler, clr, set, flags); \ clr 1121 include/linux/irq.h u32 msk, unsigned int clr, clr 1124 include/linux/irq.h irq_remove_generic_chip(gc, msk, clr, set); clr 8422 include/linux/mlx5/mlx5_ifc.h u8 clr[0x1]; clr 8481 include/linux/mlx5/mlx5_ifc.h u8 clr[0x1]; clr 400 include/soc/tegra/bpmp-abi.h uint32_t clr; clr 2129 include/soc/tegra/bpmp-abi.h int32_t clr; clr 49 include/trace/events/thp.h TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set), clr 50 include/trace/events/thp.h TP_ARGS(addr, pte, clr, set), clr 54 include/trace/events/thp.h __field(unsigned long, clr) clr 61 include/trace/events/thp.h __entry->clr = clr; clr 66 include/trace/events/thp.h TP_printk("hugepage update at addr 0x%lx and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, __entry->clr, __entry->set) clr 1094 kernel/irq/chip.c void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) clr 1108 kernel/irq/chip.c irq_settings_clr_and_set(desc, clr, set); clr 236 kernel/irq/devres.c unsigned int clr; clr 244 kernel/irq/devres.c irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); clr 264 kernel/irq/devres.c unsigned int clr, unsigned int set) clr 273 kernel/irq/devres.c irq_setup_generic_chip(gc, msk, flags, clr, set); clr 277 kernel/irq/devres.c dr->clr = clr; clr 285 kernel/irq/generic-chip.c unsigned int clr, unsigned int set, clr 311 kernel/irq/generic-chip.c dgc->irq_flags_to_clear = clr; clr 467 kernel/irq/generic-chip.c enum irq_gc_flags flags, unsigned int clr, clr 498 kernel/irq/generic-chip.c irq_modify_status(i, clr, set); clr 538 kernel/irq/generic-chip.c unsigned int clr, unsigned int set) clr 554 kernel/irq/generic-chip.c irq_modify_status(i, clr, set); clr 38 kernel/irq/settings.h irq_settings_clr_and_set(struct irq_desc *desc, u32 clr, u32 set) clr 40 kernel/irq/settings.h desc->status_use_accessors &= ~(clr & _IRQF_MODIFY_MASK); clr 162 sound/soc/bcm/bcm2835-i2s.c uint32_t clr; clr 167 sound/soc/bcm/bcm2835-i2s.c clr = tx ? BCM2835_I2S_TXCLR : 0; clr 168 sound/soc/bcm/bcm2835-i2s.c clr |= rx ? BCM2835_I2S_RXCLR : 0; clr 186 sound/soc/bcm/bcm2835-i2s.c regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);