clocks 209 arch/arm/mach-ep93xx/clock.c static struct clk_lookup clocks[] = { clocks 585 arch/arm/mach-ep93xx/clock.c clkdev_add_table(clocks, ARRAY_SIZE(clocks)); clocks 33 arch/arm/mach-omap1/clock.c static LIST_HEAD(clocks); clocks 809 arch/arm/mach-omap1/clock.c list_add(&clk->node, &clocks); clocks 834 arch/arm/mach-omap1/clock.c list_for_each_entry(clkp, &clocks, node) clocks 854 arch/arm/mach-omap1/clock.c list_for_each_entry(c, &clocks, node) { clocks 873 arch/arm/mach-omap1/clock.c list_for_each_entry(c, &clocks, node) clocks 889 arch/arm/mach-omap1/clock.c list_for_each_entry(c, &clocks, node) clocks 941 arch/arm/mach-omap1/clock.c list_for_each_entry(ck, &clocks, node) { clocks 977 arch/arm/mach-omap1/clock.c list_for_each_entry(c, &clocks, node) { clocks 1022 arch/arm/mach-omap1/clock.c list_for_each_entry(c, &clocks, node) clocks 128 arch/c6x/include/asm/clock.h extern void c6x_clks_init(struct clk_lookup *clocks); clocks 23 arch/c6x/platforms/pll.c static LIST_HEAD(clocks); clocks 166 arch/c6x/platforms/pll.c list_add_tail(&clk->node, &clocks); clocks 344 arch/c6x/platforms/pll.c void __init c6x_clks_init(struct clk_lookup *clocks) clocks 350 arch/c6x/platforms/pll.c for (c = clocks; c->clk; c++) { clocks 362 arch/c6x/platforms/pll.c clkdev_add_table(clocks, num_clocks); clocks 412 arch/c6x/platforms/pll.c list_for_each_entry(clk, &clocks, node) clocks 240 arch/mips/ar7/clock.c struct tnetd7300_clocks *clocks = clocks 245 arch/mips/ar7/clock.c &clocks->bus, bootcr, AR7_AFE_CLOCK); clocks 249 arch/mips/ar7/clock.c &clocks->cpu, bootcr, AR7_AFE_CLOCK); clocks 254 arch/mips/ar7/clock.c tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp, clocks 257 arch/mips/ar7/clock.c iounmap(clocks); clocks 324 arch/mips/ar7/clock.c struct tnetd7200_clocks *clocks = clocks 342 arch/mips/ar7/clock.c tnetd7200_set_clock(dsp_base, &clocks->dsp, clocks 351 arch/mips/ar7/clock.c tnetd7200_set_clock(cpu_base, &clocks->cpu, clocks 364 arch/mips/ar7/clock.c tnetd7200_set_clock(cpu_base, &clocks->cpu, clocks 372 arch/mips/ar7/clock.c tnetd7200_set_clock(dsp_base, &clocks->dsp, clocks 383 arch/mips/ar7/clock.c tnetd7200_set_clock(dsp_base, &clocks->dsp, clocks 394 arch/mips/ar7/clock.c tnetd7200_set_clock(usb_base, &clocks->usb, clocks 400 arch/mips/ar7/clock.c iounmap(clocks); clocks 391 arch/powerpc/platforms/52xx/mpc52xx_gpt.c u64 clocks; clocks 407 arch/powerpc/platforms/52xx/mpc52xx_gpt.c clocks = period * (u64)gpt->ipb_freq; clocks 408 arch/powerpc/platforms/52xx/mpc52xx_gpt.c do_div(clocks, 1000000000); /* Scale it down to ns range */ clocks 411 arch/powerpc/platforms/52xx/mpc52xx_gpt.c if (clocks > 0xffffffff) clocks 426 arch/powerpc/platforms/52xx/mpc52xx_gpt.c prescale = (clocks >> 16) + 1; clocks 427 arch/powerpc/platforms/52xx/mpc52xx_gpt.c do_div(clocks, prescale); clocks 428 arch/powerpc/platforms/52xx/mpc52xx_gpt.c if (clocks > 0xffff) { clocks 430 arch/powerpc/platforms/52xx/mpc52xx_gpt.c prescale, clocks); clocks 442 arch/powerpc/platforms/52xx/mpc52xx_gpt.c out_be32(&gpt->regs->count, prescale << 16 | clocks); clocks 54 arch/unicore32/kernel/clock.c static LIST_HEAD(clocks); clocks 62 arch/unicore32/kernel/clock.c list_for_each_entry(p, &clocks, node) { clocks 217 arch/unicore32/kernel/clock.c list_add(&clk->node, &clocks); clocks 330 arch/x86/kernel/apic/apic.c static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) clocks 367 arch/x86/kernel/apic/apic.c apic_write(APIC_TMICT, clocks / APIC_DIVISOR); clocks 142 drivers/ata/pata_atp867x.c unsigned char clocks = clk; clocks 149 drivers/ata/pata_atp867x.c clocks++; clocks 151 drivers/ata/pata_atp867x.c switch (clocks) { clocks 153 drivers/ata/pata_atp867x.c clocks = 1; clocks 162 drivers/ata/pata_atp867x.c clocks = 7; /* 12 clk */ clocks 166 drivers/ata/pata_atp867x.c clocks = 0; clocks 171 drivers/ata/pata_atp867x.c return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT; clocks 176 drivers/ata/pata_atp867x.c unsigned char clocks = clk; clocks 178 drivers/ata/pata_atp867x.c switch (clocks) { clocks 180 drivers/ata/pata_atp867x.c clocks = 1; clocks 186 drivers/ata/pata_atp867x.c --clocks; /* by the spec */ clocks 195 drivers/ata/pata_atp867x.c clocks = 0; clocks 199 drivers/ata/pata_atp867x.c return clocks << ATP867X_IO_PIOSPD_RECOVER_SHIFT; clocks 125 drivers/ata/pata_hpt366.c struct hpt_clock *clocks = ap->host->private_data; clocks 127 drivers/ata/pata_hpt366.c while (clocks->xfer_mode) { clocks 128 drivers/ata/pata_hpt366.c if (clocks->xfer_mode == speed) clocks 129 drivers/ata/pata_hpt366.c return clocks->timing; clocks 130 drivers/ata/pata_hpt366.c clocks++; clocks 39 drivers/ata/pata_hpt37x.c struct hpt_clock const *clocks[4]; clocks 213 drivers/ata/pata_hpt37x.c struct hpt_clock *clocks = ap->host->private_data; clocks 215 drivers/ata/pata_hpt37x.c while (clocks->xfer_speed) { clocks 216 drivers/ata/pata_hpt37x.c if (clocks->xfer_speed == speed) clocks 217 drivers/ata/pata_hpt37x.c return clocks->timing; clocks 218 drivers/ata/pata_hpt37x.c clocks++; clocks 972 drivers/ata/pata_hpt37x.c if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { clocks 1021 drivers/ata/pata_hpt37x.c private_data = (void *)chip_table->clocks[clock_slot]; clocks 45 drivers/ata/pata_hpt3x2n.c struct hpt_clock *clocks[3]; clocks 106 drivers/ata/pata_hpt3x2n.c struct hpt_clock *clocks = hpt3x2n_clocks; clocks 108 drivers/ata/pata_hpt3x2n.c while (clocks->xfer_speed) { clocks 109 drivers/ata/pata_hpt3x2n.c if (clocks->xfer_speed == speed) clocks 110 drivers/ata/pata_hpt3x2n.c return clocks->timing; clocks 111 drivers/ata/pata_hpt3x2n.c clocks++; clocks 86 drivers/bus/ti-sysc.c struct clk **clocks; clocks 271 drivers/bus/ti-sysc.c if (!ddata->clocks[i]) { clocks 283 drivers/bus/ti-sysc.c ddata->clocks[index] = devm_clk_get(ddata->dev, name); clocks 284 drivers/bus/ti-sysc.c if (IS_ERR(ddata->clocks[index])) { clocks 286 drivers/bus/ti-sysc.c name, PTR_ERR(ddata->clocks[index])); clocks 288 drivers/bus/ti-sysc.c return PTR_ERR(ddata->clocks[index]); clocks 291 drivers/bus/ti-sysc.c error = clk_prepare(ddata->clocks[index]); clocks 352 drivers/bus/ti-sysc.c ddata->clocks = devm_kcalloc(ddata->dev, clocks 353 drivers/bus/ti-sysc.c ddata->nr_clocks, sizeof(*ddata->clocks), clocks 355 drivers/bus/ti-sysc.c if (!ddata->clocks) clocks 377 drivers/bus/ti-sysc.c if (!ddata->clocks) clocks 381 drivers/bus/ti-sysc.c clock = ddata->clocks[i]; clocks 396 drivers/bus/ti-sysc.c clock = ddata->clocks[i]; clocks 413 drivers/bus/ti-sysc.c if (!ddata->clocks) clocks 417 drivers/bus/ti-sysc.c clock = ddata->clocks[i]; clocks 430 drivers/bus/ti-sysc.c if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) clocks 434 drivers/bus/ti-sysc.c clock = ddata->clocks[i]; clocks 449 drivers/bus/ti-sysc.c clock = ddata->clocks[i]; clocks 464 drivers/bus/ti-sysc.c if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) clocks 468 drivers/bus/ti-sysc.c clock = ddata->clocks[i]; clocks 1532 drivers/bus/ti-sysc.c ick = ddata->clocks[SYSC_ICK]; clocks 1535 drivers/bus/ti-sysc.c fck = ddata->clocks[SYSC_FCK]; clocks 2113 drivers/bus/ti-sysc.c if (!ddata->clocks) clocks 2117 drivers/bus/ti-sysc.c if (!IS_ERR_OR_NULL(ddata->clocks[i])) clocks 2118 drivers/bus/ti-sysc.c clk_unprepare(ddata->clocks[i]); clocks 25 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal"), clocks 43 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("bbl_32k", clocks 67 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 79 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 91 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 103 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 114 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_32k"), /* Verify */ clocks 119 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_32k"), /* Verify */ clocks 124 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_32k"), /* Verify */ clocks 129 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_32k"), /* Verify */ clocks 164 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 174 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 184 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 194 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 205 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 216 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 227 drivers/clk/bcm/clk-bcm21664.c .clocks = CLOCKS("ref_crystal", clocks 27 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal"), clocks 43 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("bbl_32k", clocks 52 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 61 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("var_312m", clocks 85 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 104 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 116 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 128 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 140 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 152 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 163 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 175 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 208 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 218 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 228 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 238 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 248 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 260 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 272 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 283 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 294 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 305 drivers/clk/bcm/clk-bcm281xx.c .clocks = CLOCKS("ref_crystal", clocks 535 drivers/clk/bcm/clk-kona-setup.c static u32 *parent_process(const char *clocks[], clocks 549 drivers/clk/bcm/clk-kona-setup.c if (!clocks) clocks 556 drivers/clk/bcm/clk-kona-setup.c for (clock = clocks; *clock; clock++) clocks 559 drivers/clk/bcm/clk-kona-setup.c orig_count = (u32)(clock - clocks); clocks 596 drivers/clk/bcm/clk-kona-setup.c if (clocks[i] != BAD_CLK_NAME) { clocks 597 drivers/clk/bcm/clk-kona-setup.c parent_names[j] = clocks[i]; clocks 609 drivers/clk/bcm/clk-kona-setup.c clk_sel_setup(const char **clocks, struct bcm_clk_sel *sel, clocks 630 drivers/clk/bcm/clk-kona-setup.c parent_sel = parent_process(clocks, &parent_count, &parent_names); clocks 678 drivers/clk/bcm/clk-kona-setup.c return clk_sel_setup(data->clocks, &data->sel, init_data); clocks 399 drivers/clk/bcm/clk-kona.h const char *clocks[]; /* must be last; use CLOCKS() to declare */ clocks 24 drivers/clk/clkdev.c static LIST_HEAD(clocks); clocks 48 drivers/clk/clkdev.c list_for_each_entry(p, &clocks, node) { clocks 124 drivers/clk/clkdev.c list_add_tail(&cl->node, &clocks); clocks 141 drivers/clk/clkdev.c list_add_tail(&cl->node, &clocks); clocks 142 drivers/clk/hisilicon/clk.h struct clk **clocks = data->clk_data.clks; \ clocks 146 drivers/clk/hisilicon/clk.h if (clocks[id]) \ clocks 147 drivers/clk/hisilicon/clk.h clk_unregister_##type(clocks[id]); \ clocks 621 drivers/clk/ingenic/cgu.c cgu->clocks.clks[idx] = clk; clocks 659 drivers/clk/ingenic/cgu.c parent = cgu->clocks.clks[clk_info->parents[i]]; clocks 670 drivers/clk/ingenic/cgu.c parent = cgu->clocks.clks[clk_info->parents[0]]; clocks 733 drivers/clk/ingenic/cgu.c cgu->clocks.clks[idx] = clk; clocks 758 drivers/clk/ingenic/cgu.c cgu->clocks.clk_num = num_clocks; clocks 775 drivers/clk/ingenic/cgu.c cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), clocks 777 drivers/clk/ingenic/cgu.c if (!cgu->clocks.clks) { clocks 782 drivers/clk/ingenic/cgu.c for (i = 0; i < cgu->clocks.clk_num; i++) { clocks 789 drivers/clk/ingenic/cgu.c &cgu->clocks); clocks 796 drivers/clk/ingenic/cgu.c for (i = 0; i < cgu->clocks.clk_num; i++) { clocks 797 drivers/clk/ingenic/cgu.c if (!cgu->clocks.clks[i]) clocks 800 drivers/clk/ingenic/cgu.c clk_put(cgu->clocks.clks[i]); clocks 802 drivers/clk/ingenic/cgu.c clk_unregister(cgu->clocks.clks[i]); clocks 804 drivers/clk/ingenic/cgu.c kfree(cgu->clocks.clks); clocks 185 drivers/clk/ingenic/cgu.h struct clk_onecell_data clocks; clocks 54 drivers/clk/ingenic/tcu.c struct clk_hw_onecell_data *clocks; clocks 272 drivers/clk/ingenic/tcu.c struct clk_hw_onecell_data *clocks) clocks 297 drivers/clk/ingenic/tcu.c clocks->hws[idx] = &tcu_clk->hw; clocks 361 drivers/clk/ingenic/tcu.c tcu->clocks = kzalloc(sizeof(*tcu->clocks) + clocks 362 drivers/clk/ingenic/tcu.c sizeof(*tcu->clocks->hws) * TCU_CLK_COUNT, clocks 364 drivers/clk/ingenic/tcu.c if (!tcu->clocks) { clocks 369 drivers/clk/ingenic/tcu.c tcu->clocks->num = TCU_CLK_COUNT; clocks 374 drivers/clk/ingenic/tcu.c tcu->clocks); clocks 390 drivers/clk/ingenic/tcu.c tcu->clocks); clocks 400 drivers/clk/ingenic/tcu.c tcu->clocks); clocks 407 drivers/clk/ingenic/tcu.c ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks); clocks 419 drivers/clk/ingenic/tcu.c clk_hw_unregister(tcu->clocks->hws[i + 1]); clocks 421 drivers/clk/ingenic/tcu.c clk_hw_unregister(tcu->clocks->hws[i]); clocks 423 drivers/clk/ingenic/tcu.c for (i = 0; i < tcu->clocks->num; i++) clocks 424 drivers/clk/ingenic/tcu.c if (tcu->clocks->hws[i]) clocks 425 drivers/clk/ingenic/tcu.c clk_hw_unregister(tcu->clocks->hws[i]); clocks 426 drivers/clk/ingenic/tcu.c kfree(tcu->clocks); clocks 44 drivers/clk/keystone/sci-clk.c struct sci_clk **clocks; clocks 382 drivers/clk/keystone/sci-clk.c clk = bsearch(&key, provider->clocks, provider->num_clocks, clocks 397 drivers/clk/keystone/sci-clk.c ret = _sci_clk_build(p, p->clocks[i]); clocks 475 drivers/clk/keystone/sci-clk.c provider->clocks = devm_kmalloc_array(dev, num_clks, sizeof(sci_clk), clocks 477 drivers/clk/keystone/sci-clk.c if (!provider->clocks) clocks 480 drivers/clk/keystone/sci-clk.c memcpy(provider->clocks, clks, num_clks * sizeof(sci_clk)); clocks 601 drivers/clk/keystone/sci-clk.c provider->clocks = devm_kmalloc_array(dev, num_clks, sizeof(sci_clk), clocks 603 drivers/clk/keystone/sci-clk.c if (!provider->clocks) clocks 614 drivers/clk/keystone/sci-clk.c provider->clocks[num_clks++] = sci_clk; clocks 320 drivers/clk/renesas/r9a06g032-clocks.c clk_rdesc_set(struct r9a06g032_priv *clocks, clocks 323 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); clocks 331 drivers/clk/renesas/r9a06g032-clocks.c clk_rdesc_get(struct r9a06g032_priv *clocks, clocks 334 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); clocks 347 drivers/clk/renesas/r9a06g032-clocks.c struct r9a06g032_priv *clocks; clocks 435 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, clocks 442 drivers/clk/renesas/r9a06g032-clocks.c spin_lock_irqsave(&clocks->lock, flags); clocks 443 drivers/clk/renesas/r9a06g032-clocks.c clk_rdesc_set(clocks, g->gate, on); clocks 446 drivers/clk/renesas/r9a06g032-clocks.c clk_rdesc_set(clocks, g->reset, 1); clocks 447 drivers/clk/renesas/r9a06g032-clocks.c spin_unlock_irqrestore(&clocks->lock, flags); clocks 457 drivers/clk/renesas/r9a06g032-clocks.c spin_lock_irqsave(&clocks->lock, flags); clocks 459 drivers/clk/renesas/r9a06g032-clocks.c clk_rdesc_set(clocks, g->ready, on); clocks 462 drivers/clk/renesas/r9a06g032-clocks.c clk_rdesc_set(clocks, g->midle, !on); clocks 463 drivers/clk/renesas/r9a06g032-clocks.c spin_unlock_irqrestore(&clocks->lock, flags); clocks 472 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_clk_gate_set(g->clocks, &g->gate, 1); clocks 480 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_clk_gate_set(g->clocks, &g->gate, 0); clocks 488 drivers/clk/renesas/r9a06g032-clocks.c if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset)) clocks 491 drivers/clk/renesas/r9a06g032-clocks.c return clk_rdesc_get(g->clocks, g->gate.gate); clocks 501 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_register_gate(struct r9a06g032_priv *clocks, clocks 519 drivers/clk/renesas/r9a06g032-clocks.c g->clocks = clocks; clocks 544 drivers/clk/renesas/r9a06g032-clocks.c struct r9a06g032_priv *clocks; clocks 560 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); clocks 647 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); clocks 671 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_register_div(struct r9a06g032_priv *clocks, clocks 690 drivers/clk/renesas/r9a06g032-clocks.c div->clocks = clocks; clocks 724 drivers/clk/renesas/r9a06g032-clocks.c struct r9a06g032_priv *clocks; clocks 736 drivers/clk/renesas/r9a06g032-clocks.c return clk_rdesc_get(set->clocks, set->selector); clocks 744 drivers/clk/renesas/r9a06g032-clocks.c clk_rdesc_set(set->clocks, set->selector, !!index); clocks 755 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, clocks 778 drivers/clk/renesas/r9a06g032-clocks.c g->clocks = clocks; clocks 793 drivers/clk/renesas/r9a06g032-clocks.c struct r9a06g032_priv *clocks; clocks 805 drivers/clk/renesas/r9a06g032-clocks.c u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); clocks 808 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0); clocks 809 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable); clocks 833 drivers/clk/renesas/r9a06g032-clocks.c u8 sel_bit = clk_rdesc_get(g->clocks, g->selector); clocks 835 drivers/clk/renesas/r9a06g032-clocks.c return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate); clocks 845 drivers/clk/renesas/r9a06g032-clocks.c r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, clocks 858 drivers/clk/renesas/r9a06g032-clocks.c g->clocks = clocks; clocks 899 drivers/clk/renesas/r9a06g032-clocks.c struct r9a06g032_priv *clocks; clocks 906 drivers/clk/renesas/r9a06g032-clocks.c clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL); clocks 909 drivers/clk/renesas/r9a06g032-clocks.c if (!clocks || !clks) clocks 912 drivers/clk/renesas/r9a06g032-clocks.c spin_lock_init(&clocks->lock); clocks 914 drivers/clk/renesas/r9a06g032-clocks.c clocks->data.clks = clks; clocks 915 drivers/clk/renesas/r9a06g032-clocks.c clocks->data.clk_num = R9A06G032_CLOCK_COUNT; clocks 921 drivers/clk/renesas/r9a06g032-clocks.c clocks->reg = of_iomap(np, 0); clocks 922 drivers/clk/renesas/r9a06g032-clocks.c if (WARN_ON(!clocks->reg)) clocks 927 drivers/clk/renesas/r9a06g032-clocks.c __clk_get_name(clocks->data.clks[d->source - 1]) : clocks 938 drivers/clk/renesas/r9a06g032-clocks.c clk = r9a06g032_register_gate(clocks, parent_name, d); clocks 941 drivers/clk/renesas/r9a06g032-clocks.c clk = r9a06g032_register_div(clocks, parent_name, d); clocks 946 drivers/clk/renesas/r9a06g032-clocks.c clk = r9a06g032_register_bitsel(clocks, parent_name, d); clocks 949 drivers/clk/renesas/r9a06g032-clocks.c clk = r9a06g032_register_dualgate(clocks, parent_name, clocks 954 drivers/clk/renesas/r9a06g032-clocks.c clocks->data.clks[d->index] = clk; clocks 956 drivers/clk/renesas/r9a06g032-clocks.c error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data); clocks 592 drivers/clk/rockchip/clk.c void __init rockchip_clk_protect_critical(const char *const clocks[], clocks 599 drivers/clk/rockchip/clk.c struct clk *clk = __clk_lookup(clocks[i]); clocks 849 drivers/clk/rockchip/clk.h void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); clocks 401 drivers/clk/tegra/clk-bpmp.c struct tegra_bpmp_clk_info *clocks; clocks 414 drivers/clk/tegra/clk-bpmp.c clocks = kcalloc(max_id + 1, sizeof(*clocks), GFP_KERNEL); clocks 415 drivers/clk/tegra/clk-bpmp.c if (!clocks) clocks 419 drivers/clk/tegra/clk-bpmp.c struct tegra_bpmp_clk_info *info = &clocks[count]; clocks 446 drivers/clk/tegra/clk-bpmp.c *clocksp = clocks; clocks 452 drivers/clk/tegra/clk-bpmp.c tegra_bpmp_clk_find(const struct tegra_bpmp_clk_info *clocks, clocks 458 drivers/clk/tegra/clk-bpmp.c if (clocks[i].id == id) clocks 459 drivers/clk/tegra/clk-bpmp.c return &clocks[i]; clocks 467 drivers/clk/tegra/clk-bpmp.c const struct tegra_bpmp_clk_info *clocks, clocks 519 drivers/clk/tegra/clk-bpmp.c parent = tegra_bpmp_clk_find(clocks, num_clocks, clocks 551 drivers/clk/tegra/clk-bpmp.c bpmp->clocks = devm_kcalloc(bpmp->dev, count, sizeof(clk), GFP_KERNEL); clocks 552 drivers/clk/tegra/clk-bpmp.c if (!bpmp->clocks) clocks 566 drivers/clk/tegra/clk-bpmp.c bpmp->clocks[i] = clk; clocks 577 drivers/clk/tegra/clk-bpmp.c clk_hw_unregister(&bpmp->clocks[i]->hw); clocks 587 drivers/clk/tegra/clk-bpmp.c struct tegra_bpmp_clk *clk = bpmp->clocks[i]; clocks 601 drivers/clk/tegra/clk-bpmp.c struct tegra_bpmp_clk_info *clocks; clocks 605 drivers/clk/tegra/clk-bpmp.c err = tegra_bpmp_probe_clocks(bpmp, &clocks); clocks 613 drivers/clk/tegra/clk-bpmp.c err = tegra_bpmp_register_clocks(bpmp, clocks, count); clocks 626 drivers/clk/tegra/clk-bpmp.c kfree(clocks); clocks 177 drivers/clk/ti/adpll.c struct ti_adpll_clock *clocks; clocks 221 drivers/clk/ti/adpll.c d->clocks[index].clk = clock; clocks 222 drivers/clk/ti/adpll.c d->clocks[index].unregister = unregister; clocks 234 drivers/clk/ti/adpll.c d->clocks[index].cl = cl; clocks 656 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_N2].clk, clocks 665 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_DCO].clk, clocks 675 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_M2].clk, clocks 683 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_DIV2].clk, clocks 684 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_BYPASS].clk); clocks 690 drivers/clk/ti/adpll.c "clkout2", d->clocks[TI_ADPLL_M2].clk, clocks 691 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_BYPASS].clk); clocks 698 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_DCO].clk, clocks 708 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_HIF].clk, clocks 730 drivers/clk/ti/adpll.c "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk, clocks 738 drivers/clk/ti/adpll.c "m2", d->clocks[TI_ADPLL_DCO].clk, clocks 748 drivers/clk/ti/adpll.c "clkoutldo", d->clocks[TI_ADPLL_M2].clk, clocks 757 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_N2].clk, clocks 767 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_M2].clk, clocks 768 drivers/clk/ti/adpll.c d->clocks[TI_ADPLL_BYPASS].clk); clocks 780 drivers/clk/ti/adpll.c struct ti_adpll_clock *ac = &d->clocks[i]; clocks 920 drivers/clk/ti/adpll.c d->clocks = devm_kcalloc(d->dev, clocks 924 drivers/clk/ti/adpll.c if (!d->clocks) clocks 323 drivers/clk/ti/clk.c struct device_node *clocks; clocks 327 drivers/clk/ti/clk.c clocks = of_get_child_by_name(parent, "clocks"); clocks 328 drivers/clk/ti/clk.c if (!clocks) { clocks 334 drivers/clk/ti/clk.c clocks_node_ptr[index] = clocks; clocks 49 drivers/clk/ti/clkctrl.c struct list_head clocks; clocks 241 drivers/clk/ti/clkctrl.c list_for_each_entry(entry, &provider->clocks, node) { clocks 295 drivers/clk/ti/clkctrl.c list_add(&clkctrl_clk->node, &provider->clocks); clocks 574 drivers/clk/ti/clkctrl.c INIT_LIST_HEAD(&provider->clocks); clocks 633 drivers/clk/ti/clkctrl.c list_add(&clkctrl_clk->node, &provider->clocks); clocks 45 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c static const struct cg_flag_name clocks[] = { clocks 3138 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c for (i = 0; clocks[i].flag; i++) clocks 3139 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c seq_printf(m, "\t%s: %s\n", clocks[i].name, clocks 3140 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c (flags & clocks[i].flag) ? "On" : "Off"); clocks 3219 drivers/gpu/drm/amd/amdgpu/si_dpm.c static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, clocks 3224 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((clocks == NULL) || (clocks->count == 0)) clocks 3227 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < clocks->count; i++) { clocks 3228 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (clocks->values[i] >= requested_clock) clocks 3229 drivers/gpu/drm/amd/amdgpu/si_dpm.c return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; clocks 3232 drivers/gpu/drm/amd/amdgpu/si_dpm.c return (clocks->values[clocks->count - 1] < max_clock) ? clocks 3233 drivers/gpu/drm/amd/amdgpu/si_dpm.c clocks->values[clocks->count - 1] : max_clock; clocks 1381 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c struct dc_clocks *clocks) clocks 1388 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz); clocks 1390 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz); clocks 1394 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz); clocks 1398 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz); clocks 1401 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz); clocks 35 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c #define TO_DCE_CLK_MGR(clocks)\ clocks 36 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c container_of(clocks, struct dce_clk_mgr, base) clocks 629 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h struct dc_clocks *clocks); clocks 287 drivers/gpu/drm/amd/include/kgd_pp_interface.h struct amd_pp_clock_info *clocks); clocks 290 drivers/gpu/drm/amd/include/kgd_pp_interface.h struct amd_pp_clocks *clocks); clocks 293 drivers/gpu/drm/amd/include/kgd_pp_interface.h struct pp_clock_levels_with_latency *clocks); clocks 296 drivers/gpu/drm/amd/include/kgd_pp_interface.h struct pp_clock_levels_with_voltage *clocks); clocks 302 drivers/gpu/drm/amd/include/kgd_pp_interface.h struct amd_pp_simple_clock_info *clocks); clocks 1065 drivers/gpu/drm/amd/powerplay/amd_powerplay.c struct amd_pp_clock_info *clocks) clocks 1093 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->min_engine_clock = hw_clocks.min_eng_clk; clocks 1094 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->max_engine_clock = hw_clocks.max_eng_clk; clocks 1095 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->min_memory_clock = hw_clocks.min_mem_clk; clocks 1096 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->max_memory_clock = hw_clocks.max_mem_clk; clocks 1097 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; clocks 1098 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; clocks 1100 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; clocks 1101 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; clocks 1104 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->max_clocks_state = PP_DAL_POWERLEVEL_7; clocks 1106 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->max_clocks_state = simple_clocks.level; clocks 1109 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; clocks 1110 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; clocks 1116 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) clocks 1124 drivers/gpu/drm/amd/powerplay/amd_powerplay.c if (clocks == NULL) clocks 1128 drivers/gpu/drm/amd/powerplay/amd_powerplay.c ret = phm_get_clock_by_type(hwmgr, type, clocks); clocks 1135 drivers/gpu/drm/amd/powerplay/amd_powerplay.c struct pp_clock_levels_with_latency *clocks) clocks 1140 drivers/gpu/drm/amd/powerplay/amd_powerplay.c if (!hwmgr || !hwmgr->pm_en ||!clocks) clocks 1144 drivers/gpu/drm/amd/powerplay/amd_powerplay.c ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks); clocks 1151 drivers/gpu/drm/amd/powerplay/amd_powerplay.c struct pp_clock_levels_with_voltage *clocks) clocks 1156 drivers/gpu/drm/amd/powerplay/amd_powerplay.c if (!hwmgr || !hwmgr->pm_en ||!clocks) clocks 1161 drivers/gpu/drm/amd/powerplay/amd_powerplay.c ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); clocks 1201 drivers/gpu/drm/amd/powerplay/amd_powerplay.c struct amd_pp_simple_clock_info *clocks) clocks 1206 drivers/gpu/drm/amd/powerplay/amd_powerplay.c if (!hwmgr || !hwmgr->pm_en ||!clocks) clocks 1209 drivers/gpu/drm/amd/powerplay/amd_powerplay.c clocks->level = PP_DAL_POWERLEVEL_7; clocks 1214 drivers/gpu/drm/amd/powerplay/amd_powerplay.c ret = phm_get_max_high_clocks(hwmgr, clocks); clocks 1466 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c struct amd_pp_clock_info *clocks) clocks 1490 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->min_engine_clock = hw_clocks.min_eng_clk; clocks 1491 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->max_engine_clock = hw_clocks.max_eng_clk; clocks 1492 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->min_memory_clock = hw_clocks.min_mem_clk; clocks 1493 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->max_memory_clock = hw_clocks.max_mem_clk; clocks 1494 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; clocks 1495 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; clocks 1496 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; clocks 1497 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; clocks 1500 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->max_clocks_state = PP_DAL_POWERLEVEL_7; clocks 1502 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->max_clocks_state = simple_clocks.level; clocks 1505 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; clocks 1506 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; clocks 563 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c struct pp_clock_levels_with_latency *clocks, clocks 569 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks->num_levels = count; clocks 572 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks->data[i].clocks_in_khz = clocks 574 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks->data[i].latency_in_us = 0; clocks 591 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c struct pp_clock_levels_with_latency clocks; clocks 607 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); clocks 613 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c for (i = 0; i < clocks.num_levels; i++) clocks 615 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks.data[i].clocks_in_khz / 1000, clocks 617 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks.data[i].clocks_in_khz / 1000, clocks 629 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); clocks 635 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c for (i = 0; i < clocks.num_levels; i++) clocks 637 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c i, clocks.data[i].clocks_in_khz / 1000, clocks 639 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks.data[i].clocks_in_khz / 1000, clocks 651 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); clocks 657 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c for (i = 0; i < clocks.num_levels; i++) clocks 659 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c i, clocks.data[i].clocks_in_khz / 1000, clocks 661 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks.data[i].clocks_in_khz / 1000, clocks 673 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); clocks 683 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c clocks.data[i].clocks_in_khz / 1000, clocks 411 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) clocks 418 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks); clocks 424 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c struct pp_clock_levels_with_latency *clocks) clocks 431 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks); clocks 437 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c struct pp_clock_levels_with_voltage *clocks) clocks 444 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks); clocks 471 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) clocks 478 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks); clocks 195 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c struct PP_Clocks clocks = {0}; clocks 198 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; clocks 200 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clock_req.clock_freq_in_khz = clocks.dcefClock * 10; clocks 988 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 1027 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->num_levels = 0; clocks 1030 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->data[clocks->num_levels].clocks_in_khz = clocks 1032 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->data[clocks->num_levels].latency_in_us = latency_required ? clocks 1036 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->num_levels++; clocks 1045 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c struct pp_clock_levels_with_voltage *clocks) clocks 1081 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->num_levels = 0; clocks 1084 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; clocks 1085 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; clocks 1086 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->num_levels++; clocks 1095 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) clocks 1097 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */ clocks 4651 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) clocks 4664 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; clocks 4665 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->count = dep_sclk_table->count; clocks 4669 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->clock[i] = sclk_table->entries[i].clk * 10; clocks 4670 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->count = sclk_table->count; clocks 4688 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) clocks 4701 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; clocks 4702 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->latency[i] = smu7_get_mem_latency(hwmgr, clocks 4705 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->count = dep_mclk_table->count; clocks 4709 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->clock[i] = mclk_table->entries[i].clk * 10; clocks 4710 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->count = mclk_table->count; clocks 4716 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct amd_pp_clocks *clocks) clocks 4720 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_get_sclks(hwmgr, clocks); clocks 4723 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_get_mclks(hwmgr, clocks); clocks 4774 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct amd_pp_simple_clock_info *clocks) clocks 4780 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (clocks == NULL) clocks 4783 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->memory_max_clock = mclk_table->count > 1 ? clocks 4786 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->engine_max_clock = sclk_table->count > 1 ? clocks 1046 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct PP_Clocks clocks = {0, 0, 0, 0}; clocks 1053 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? clocks 1059 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; clocks 1061 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]) clocks 1602 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct amd_pp_clocks *clocks) clocks 1608 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->count = smu8_get_max_sclk_level(hwmgr); clocks 1611 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c for (i = 0; i < clocks->count; i++) clocks 1612 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->clock[i] = data->sys_info.display_clock[i] * 10; clocks 1616 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c for (i = 0; i < clocks->count; i++) clocks 1617 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->clock[i] = table->entries[i].clk * 10; clocks 1620 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->count = SMU8_NUM_NBPMEMORYCLOCK; clocks 1621 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c for (i = 0; i < clocks->count; i++) clocks 1622 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10; clocks 1631 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) clocks 1639 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c if ((NULL == table) || (table->count <= 0) || (clocks == NULL)) clocks 1645 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->engine_max_clock = table->entries[level].clk; clocks 1647 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->engine_max_clock = table->entries[table->count - 1].clk; clocks 1649 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c clocks->memory_max_clock = limits->mclk; clocks 4209 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 4217 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->num_levels = 0; clocks 4220 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[clocks->num_levels].clocks_in_khz = clocks 4222 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->num_levels++; clocks 4229 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 4242 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[j].clocks_in_khz = clocks 4246 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[j].latency_in_us = clocks 4251 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->num_levels = data->mclk_latency_table.count = j; clocks 4255 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 4264 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; clocks 4265 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 4266 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->num_levels++; clocks 4271 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 4280 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; clocks 4281 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 4282 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->num_levels++; clocks 4288 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 4292 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c vega10_get_sclks(hwmgr, clocks); clocks 4295 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c vega10_get_memclocks(hwmgr, clocks); clocks 4298 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c vega10_get_dcefclocks(hwmgr, clocks); clocks 4301 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c vega10_get_socclocks(hwmgr, clocks); clocks 4312 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct pp_clock_levels_with_voltage *clocks) clocks 4340 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; clocks 4341 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table-> clocks 4343 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c clocks->num_levels++; clocks 1711 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 1726 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].clocks_in_khz = clocks 1729 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 1732 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->num_levels = ucount; clocks 1744 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 1758 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; clocks 1760 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].latency_in_us = clocks 1765 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->num_levels = data->mclk_latency_table.count = ucount; clocks 1771 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 1787 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].clocks_in_khz = clocks 1790 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 1793 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->num_levels = ucount; clocks 1799 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 1815 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].clocks_in_khz = clocks 1818 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 1821 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->num_levels = ucount; clocks 1829 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 1835 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_sclks(hwmgr, clocks); clocks 1838 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_memclocks(hwmgr, clocks); clocks 1841 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_dcefclocks(hwmgr, clocks); clocks 1844 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ret = vega12_get_socclocks(hwmgr, clocks); clocks 1855 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct pp_clock_levels_with_voltage *clocks) clocks 1857 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c clocks->num_levels = 0; clocks 2091 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct pp_clock_levels_with_latency clocks; clocks 2101 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c vega12_get_sclks(hwmgr, &clocks) == 0, clocks 2104 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 2106 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 2107 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); clocks 2117 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c vega12_get_memclocks(hwmgr, &clocks) == 0, clocks 2120 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 2122 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 2123 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); clocks 2135 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c vega12_get_socclocks(hwmgr, &clocks) == 0, clocks 2138 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 2140 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 2141 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); clocks 2153 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c vega12_get_dcefclocks(hwmgr, &clocks) == 0, clocks 2156 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 2158 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 2159 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); clocks 2755 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 2765 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->num_levels = count; clocks 2768 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].clocks_in_khz = clocks 2770 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 2783 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 2793 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->num_levels = data->mclk_latency_table.count = count; clocks 2796 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].clocks_in_khz = clocks 2799 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].latency_in_us = clocks 2808 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 2818 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->num_levels = count; clocks 2821 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].clocks_in_khz = clocks 2823 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 2830 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 2840 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->num_levels = count; clocks 2843 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].clocks_in_khz = clocks 2845 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->data[i].latency_in_us = 0; clocks 2854 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_clock_levels_with_latency *clocks) clocks 2860 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ret = vega20_get_sclks(hwmgr, clocks); clocks 2863 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ret = vega20_get_memclocks(hwmgr, clocks); clocks 2866 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ret = vega20_get_dcefclocks(hwmgr, clocks); clocks 2869 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ret = vega20_get_socclocks(hwmgr, clocks); clocks 2880 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_clock_levels_with_voltage *clocks) clocks 2882 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c clocks->num_levels = 0; clocks 3262 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct pp_clock_levels_with_latency clocks; clocks 3276 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c if (vega20_get_sclks(hwmgr, &clocks)) { clocks 3282 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 3284 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 3285 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); clocks 3294 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c if (vega20_get_memclocks(hwmgr, &clocks)) { clocks 3300 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 3302 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 3303 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); clocks 3312 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c if (vega20_get_socclocks(hwmgr, &clocks)) { clocks 3318 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 3320 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 3321 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); clocks 3342 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c if (vega20_get_dcefclocks(hwmgr, &clocks)) { clocks 3348 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c for (i = 0; i < clocks.num_levels; i++) clocks 3350 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c i, clocks.data[i].clocks_in_khz / 1000, clocks 3351 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); clocks 422 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h *clocks); clocks 427 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h *clocks); clocks 512 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h struct amd_pp_clocks *clocks); clocks 514 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h struct amd_pp_simple_clock_info *clocks); clocks 519 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h struct amd_pp_simple_clock_info *clocks); clocks 524 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h struct smu_clock_info *clocks); clocks 711 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clock_by_type(smu, type, clocks) \ clocks 712 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0) clocks 713 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_max_high_clocks(smu, clocks) \ clocks 714 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0) clocks 715 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clock_by_type_with_latency(smu, clk_type, clocks) \ clocks 716 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (clk_type), (clocks)) : 0) clocks 717 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \ clocks 718 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0) clocks 723 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_dal_power_level(smu, clocks) \ clocks 724 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0) clocks 727 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_current_shallow_sleep_clocks(smu, clocks) \ clocks 728 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0) clocks 809 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h struct amd_pp_clock_info *clocks); clocks 450 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); clocks 454 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h struct pp_clock_levels_with_latency *clocks); clocks 457 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h struct pp_clock_levels_with_voltage *clocks); clocks 463 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); clocks 302 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); clocks 305 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h struct pp_clock_levels_with_latency *clocks); clocks 308 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h struct pp_clock_levels_with_voltage *clocks); clocks 312 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); clocks 812 drivers/gpu/drm/amd/powerplay/navi10_ppt.c struct pp_clock_levels_with_latency *clocks) clocks 826 drivers/gpu/drm/amd/powerplay/navi10_ppt.c clocks->num_levels = level_count; clocks 833 drivers/gpu/drm/amd/powerplay/navi10_ppt.c clocks->data[i].clocks_in_khz = freq * 1000; clocks 834 drivers/gpu/drm/amd/powerplay/navi10_ppt.c clocks->data[i].latency_in_us = 0; clocks 923 drivers/gpu/drm/amd/powerplay/vega20_ppt.c struct pp_clock_levels_with_latency *clocks, clocks 929 drivers/gpu/drm/amd/powerplay/vega20_ppt.c clocks->num_levels = count; clocks 932 drivers/gpu/drm/amd/powerplay/vega20_ppt.c clocks->data[i].clocks_in_khz = clocks 934 drivers/gpu/drm/amd/powerplay/vega20_ppt.c clocks->data[i].latency_in_us = 0; clocks 947 drivers/gpu/drm/amd/powerplay/vega20_ppt.c struct pp_clock_levels_with_latency clocks; clocks 969 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, &clocks, single_dpm_table); clocks 975 drivers/gpu/drm/amd/powerplay/vega20_ppt.c for (i = 0; i < clocks.num_levels; i++) clocks 977 drivers/gpu/drm/amd/powerplay/vega20_ppt.c clocks.data[i].clocks_in_khz / 1000, clocks 978 drivers/gpu/drm/amd/powerplay/vega20_ppt.c (clocks.data[i].clocks_in_khz == now * 10) clocks 990 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, &clocks, single_dpm_table); clocks 996 drivers/gpu/drm/amd/powerplay/vega20_ppt.c for (i = 0; i < clocks.num_levels; i++) clocks 998 drivers/gpu/drm/amd/powerplay/vega20_ppt.c i, clocks.data[i].clocks_in_khz / 1000, clocks 999 drivers/gpu/drm/amd/powerplay/vega20_ppt.c (clocks.data[i].clocks_in_khz == now * 10) clocks 1011 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, &clocks, single_dpm_table); clocks 1017 drivers/gpu/drm/amd/powerplay/vega20_ppt.c for (i = 0; i < clocks.num_levels; i++) clocks 1019 drivers/gpu/drm/amd/powerplay/vega20_ppt.c i, clocks.data[i].clocks_in_khz / 1000, clocks 1020 drivers/gpu/drm/amd/powerplay/vega20_ppt.c (clocks.data[i].clocks_in_khz == now * 10) clocks 1047 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, &clocks, single_dpm_table); clocks 1053 drivers/gpu/drm/amd/powerplay/vega20_ppt.c for (i = 0; i < clocks.num_levels; i++) clocks 1055 drivers/gpu/drm/amd/powerplay/vega20_ppt.c i, clocks.data[i].clocks_in_khz / 1000, clocks 1056 drivers/gpu/drm/amd/powerplay/vega20_ppt.c (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); clocks 1138 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, &clocks, single_dpm_table); clocks 1145 drivers/gpu/drm/amd/powerplay/vega20_ppt.c clocks.data[0].clocks_in_khz / 1000, clocks 1445 drivers/gpu/drm/amd/powerplay/vega20_ppt.c struct pp_clock_levels_with_latency *clocks) clocks 1459 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, clocks, single_dpm_table); clocks 1463 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, clocks, single_dpm_table); clocks 1467 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, clocks, single_dpm_table); clocks 1471 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, clocks, single_dpm_table); clocks 2624 drivers/gpu/drm/amd/powerplay/vega20_ppt.c struct pp_clock_levels_with_latency clocks; clocks 2686 drivers/gpu/drm/amd/powerplay/vega20_ppt.c ret = vega20_get_clk_table(smu, &clocks, single_dpm_table); clocks 2708 drivers/gpu/drm/amd/powerplay/vega20_ppt.c if (input_clk < clocks.data[0].clocks_in_khz / 1000 || clocks 2712 drivers/gpu/drm/amd/powerplay/vega20_ppt.c clocks.data[0].clocks_in_khz / 1000, clocks 109 drivers/gpu/drm/exynos/exynos_drm_fimc.c struct clk *clocks[FIMC_CLKS_MAX]; clocks 1170 drivers/gpu/drm/exynos/exynos_drm_fimc.c if (IS_ERR(ctx->clocks[i])) clocks 1172 drivers/gpu/drm/exynos/exynos_drm_fimc.c clk_put(ctx->clocks[i]); clocks 1173 drivers/gpu/drm/exynos/exynos_drm_fimc.c ctx->clocks[i] = ERR_PTR(-EINVAL); clocks 1184 drivers/gpu/drm/exynos/exynos_drm_fimc.c ctx->clocks[i] = ERR_PTR(-EINVAL); clocks 1192 drivers/gpu/drm/exynos/exynos_drm_fimc.c ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); clocks 1193 drivers/gpu/drm/exynos/exynos_drm_fimc.c if (IS_ERR(ctx->clocks[i])) { clocks 1194 drivers/gpu/drm/exynos/exynos_drm_fimc.c ret = PTR_ERR(ctx->clocks[i]); clocks 1201 drivers/gpu/drm/exynos/exynos_drm_fimc.c ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]); clocks 1390 drivers/gpu/drm/exynos/exynos_drm_fimc.c clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); clocks 1399 drivers/gpu/drm/exynos/exynos_drm_fimc.c return clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); clocks 109 drivers/gpu/drm/exynos/exynos_drm_gsc.c struct clk *clocks[GSC_MAX_CLOCKS]; clocks 1261 drivers/gpu/drm/exynos/exynos_drm_gsc.c ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]); clocks 1262 drivers/gpu/drm/exynos/exynos_drm_gsc.c if (IS_ERR(ctx->clocks[i])) { clocks 1265 drivers/gpu/drm/exynos/exynos_drm_gsc.c return PTR_ERR(ctx->clocks[i]); clocks 1332 drivers/gpu/drm/exynos/exynos_drm_gsc.c clk_disable_unprepare(ctx->clocks[i]); clocks 1345 drivers/gpu/drm/exynos/exynos_drm_gsc.c ret = clk_prepare_enable(ctx->clocks[i]); clocks 1348 drivers/gpu/drm/exynos/exynos_drm_gsc.c clk_disable_unprepare(ctx->clocks[i]); clocks 645 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct psb_intel_sdvo_pixel_clock_range clocks; clocks 647 drivers/gpu/drm/gma500/psb_intel_sdvo.c BUILD_BUG_ON(sizeof(clocks) != 4); clocks 650 drivers/gpu/drm/gma500/psb_intel_sdvo.c &clocks, sizeof(clocks))) clocks 654 drivers/gpu/drm/gma500/psb_intel_sdvo.c *clock_min = clocks.min * 10; clocks 655 drivers/gpu/drm/gma500/psb_intel_sdvo.c *clock_max = clocks.max * 10; clocks 724 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_sdvo_pixel_clock_range clocks; clocks 726 drivers/gpu/drm/i915/display/intel_sdvo.c BUILD_BUG_ON(sizeof(clocks) != 4); clocks 729 drivers/gpu/drm/i915/display/intel_sdvo.c &clocks, sizeof(clocks))) clocks 733 drivers/gpu/drm/i915/display/intel_sdvo.c *clock_min = clocks.min * 10; clocks 734 drivers/gpu/drm/i915/display/intel_sdvo.c *clock_max = clocks.max * 10; clocks 710 drivers/gpu/drm/msm/adreno/a6xx_gmu.c ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); clocks 871 drivers/gpu/drm/msm/adreno/a6xx_gmu.c clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); clocks 1175 drivers/gpu/drm/msm/adreno/a6xx_gmu.c int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); clocks 1182 drivers/gpu/drm/msm/adreno/a6xx_gmu.c gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, clocks 63 drivers/gpu/drm/msm/adreno/a6xx_gmu.h struct clk_bulk_data *clocks; clocks 1212 drivers/gpu/drm/radeon/btc_dpm.c static u32 btc_find_valid_clock(struct radeon_clock_array *clocks, clocks 1217 drivers/gpu/drm/radeon/btc_dpm.c if ((clocks == NULL) || (clocks->count == 0)) clocks 1220 drivers/gpu/drm/radeon/btc_dpm.c for (i = 0; i < clocks->count; i++) { clocks 1221 drivers/gpu/drm/radeon/btc_dpm.c if (clocks->values[i] >= requested_clock) clocks 1222 drivers/gpu/drm/radeon/btc_dpm.c return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; clocks 1225 drivers/gpu/drm/radeon/btc_dpm.c return (clocks->values[clocks->count - 1] < max_clock) ? clocks 1226 drivers/gpu/drm/radeon/btc_dpm.c clocks->values[clocks->count - 1] : max_clock; clocks 66 drivers/gpu/drm/rcar-du/rcar_lvds.c } clocks; clocks 327 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll, clocks 329 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll, clocks 331 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, clocks 376 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = clk_prepare_enable(lvds->clocks.mod); clocks 397 drivers/gpu/drm/rcar-du/rcar_lvds.c clk_disable_unprepare(lvds->clocks.mod); clocks 413 drivers/gpu/drm/rcar-du/rcar_lvds.c ret = clk_prepare_enable(lvds->clocks.mod); clocks 540 drivers/gpu/drm/rcar-du/rcar_lvds.c clk_disable_unprepare(lvds->clocks.mod); clocks 813 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false); clocks 814 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.mod)) clocks 815 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.mod); clocks 823 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true); clocks 824 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.extal)) clocks 825 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.extal); clocks 827 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true); clocks 828 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.dotclkin[0])) clocks 829 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.dotclkin[0]); clocks 831 drivers/gpu/drm/rcar-du/rcar_lvds.c lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true); clocks 832 drivers/gpu/drm/rcar-du/rcar_lvds.c if (IS_ERR(lvds->clocks.dotclkin[1])) clocks 833 drivers/gpu/drm/rcar-du/rcar_lvds.c return PTR_ERR(lvds->clocks.dotclkin[1]); clocks 836 drivers/gpu/drm/rcar-du/rcar_lvds.c if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] && clocks 837 drivers/gpu/drm/rcar-du/rcar_lvds.c !lvds->clocks.dotclkin[1]) { clocks 104 drivers/iommu/rockchip-iommu.c struct clk_bulk_data *clocks; clocks 533 drivers/iommu/rockchip-iommu.c if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) clocks 582 drivers/iommu/rockchip-iommu.c clk_bulk_disable(iommu->num_clocks, iommu->clocks); clocks 637 drivers/iommu/rockchip-iommu.c iommu->clocks)); clocks 639 drivers/iommu/rockchip-iommu.c clk_bulk_disable(iommu->num_clocks, iommu->clocks); clocks 850 drivers/iommu/rockchip-iommu.c WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); clocks 858 drivers/iommu/rockchip-iommu.c clk_bulk_disable(iommu->num_clocks, iommu->clocks); clocks 868 drivers/iommu/rockchip-iommu.c ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); clocks 892 drivers/iommu/rockchip-iommu.c clk_bulk_disable(iommu->num_clocks, iommu->clocks); clocks 1178 drivers/iommu/rockchip-iommu.c iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, clocks 1179 drivers/iommu/rockchip-iommu.c sizeof(*iommu->clocks), GFP_KERNEL); clocks 1180 drivers/iommu/rockchip-iommu.c if (!iommu->clocks) clocks 1184 drivers/iommu/rockchip-iommu.c iommu->clocks[i].id = rk_iommu_clocks[i]; clocks 1191 drivers/iommu/rockchip-iommu.c err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); clocks 1197 drivers/iommu/rockchip-iommu.c err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); clocks 1250 drivers/iommu/rockchip-iommu.c clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); clocks 16 drivers/irqchip/irq-gic-pm.c const char *const *clocks; clocks 96 drivers/irqchip/irq-gic-pm.c chip_pm->clks[i].id = data->clocks[i]; clocks 144 drivers/irqchip/irq-gic-pm.c .clocks = gic400_clocks, clocks 294 drivers/media/i2c/cx25840/cx25840-ir.c u64 clocks; clocks 296 drivers/media/i2c/cx25840/cx25840-ir.c clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ clocks 297 drivers/media/i2c/cx25840/cx25840-ir.c rem = do_div(clocks, 1000); /* /1000 = cycles */ clocks 299 drivers/media/i2c/cx25840/cx25840-ir.c clocks++; clocks 300 drivers/media/i2c/cx25840/cx25840-ir.c return clocks; clocks 307 drivers/media/pci/cx23885/cx23888-ir.c u64 clocks; clocks 309 drivers/media/pci/cx23885/cx23888-ir.c clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */ clocks 310 drivers/media/pci/cx23885/cx23888-ir.c rem = do_div(clocks, 1000); /* /1000 = cycles */ clocks 312 drivers/media/pci/cx23885/cx23888-ir.c clocks++; clocks 313 drivers/media/pci/cx23885/cx23888-ir.c return clocks; clocks 71 drivers/media/platform/exynos4-is/fimc-is.c if (IS_ERR(is->clocks[i])) clocks 73 drivers/media/platform/exynos4-is/fimc-is.c clk_put(is->clocks[i]); clocks 74 drivers/media/platform/exynos4-is/fimc-is.c is->clocks[i] = ERR_PTR(-EINVAL); clocks 83 drivers/media/platform/exynos4-is/fimc-is.c is->clocks[i] = ERR_PTR(-EINVAL); clocks 86 drivers/media/platform/exynos4-is/fimc-is.c is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]); clocks 87 drivers/media/platform/exynos4-is/fimc-is.c if (IS_ERR(is->clocks[i])) { clocks 88 drivers/media/platform/exynos4-is/fimc-is.c ret = PTR_ERR(is->clocks[i]); clocks 105 drivers/media/platform/exynos4-is/fimc-is.c ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200], clocks 106 drivers/media/platform/exynos4-is/fimc-is.c is->clocks[ISS_CLK_ACLK200_DIV]); clocks 110 drivers/media/platform/exynos4-is/fimc-is.c ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP], clocks 111 drivers/media/platform/exynos4-is/fimc-is.c is->clocks[ISS_CLK_ACLK400MCUISP_DIV]); clocks 115 drivers/media/platform/exynos4-is/fimc-is.c ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY); clocks 119 drivers/media/platform/exynos4-is/fimc-is.c ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY); clocks 123 drivers/media/platform/exynos4-is/fimc-is.c ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0], clocks 128 drivers/media/platform/exynos4-is/fimc-is.c return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1], clocks 137 drivers/media/platform/exynos4-is/fimc-is.c if (IS_ERR(is->clocks[i])) clocks 139 drivers/media/platform/exynos4-is/fimc-is.c ret = clk_prepare_enable(is->clocks[i]); clocks 144 drivers/media/platform/exynos4-is/fimc-is.c clk_disable(is->clocks[i]); clocks 157 drivers/media/platform/exynos4-is/fimc-is.c if (!IS_ERR(is->clocks[i])) { clocks 158 drivers/media/platform/exynos4-is/fimc-is.c clk_disable_unprepare(is->clocks[i]); clocks 263 drivers/media/platform/exynos4-is/fimc-is.h struct clk *clocks[ISS_CLKS_MAX]; clocks 2906 drivers/media/platform/s5p-jpeg/jpeg-core.c jpeg->clocks[i] = devm_clk_get(&pdev->dev, clocks 2908 drivers/media/platform/s5p-jpeg/jpeg-core.c if (IS_ERR(jpeg->clocks[i])) { clocks 2911 drivers/media/platform/s5p-jpeg/jpeg-core.c return PTR_ERR(jpeg->clocks[i]); clocks 3028 drivers/media/platform/s5p-jpeg/jpeg-core.c clk_disable_unprepare(jpeg->clocks[i]); clocks 3041 drivers/media/platform/s5p-jpeg/jpeg-core.c clk_disable_unprepare(jpeg->clocks[i]); clocks 3053 drivers/media/platform/s5p-jpeg/jpeg-core.c ret = clk_prepare_enable(jpeg->clocks[i]); clocks 3056 drivers/media/platform/s5p-jpeg/jpeg-core.c clk_disable_unprepare(jpeg->clocks[i]); clocks 133 drivers/media/platform/s5p-jpeg/jpeg-core.h struct clk *clocks[JPEG_MAX_CLOCKS]; clocks 196 drivers/media/platform/s5p-mfc/s5p_mfc_common.h struct clk *clocks[MFC_MAX_CLOCKS]; clocks 35 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c pm->clocks[i] = devm_clk_get(pm->device, pm->clk_names[i]); clocks 36 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c if (IS_ERR(pm->clocks[i])) { clocks 38 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c if (i && PTR_ERR(pm->clocks[i]) == -ENOENT) { clocks 39 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c pm->clocks[i] = NULL; clocks 44 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c return PTR_ERR(pm->clocks[i]); clocks 49 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c pm->clock_gate = pm->clocks[0]; clocks 87 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c ret = clk_prepare_enable(pm->clocks[i]); clocks 102 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c clk_disable_unprepare(pm->clocks[i]); clocks 115 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c clk_disable_unprepare(pm->clocks[i]); clocks 85 drivers/mfd/asic3.c struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)]; clocks 661 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); clocks 662 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); clocks 663 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); clocks 687 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); clocks 688 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); clocks 689 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); clocks 752 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); clocks 756 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); clocks 763 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); clocks 764 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); clocks 790 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); clocks 791 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); clocks 792 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); clocks 793 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); clocks 820 drivers/mfd/asic3.c asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]); clocks 830 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); clocks 843 drivers/mfd/asic3.c asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); clocks 1015 drivers/mfd/asic3.c memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); clocks 155 drivers/net/hamradio/dmascc.c int clocks; /* see dmascc_cfg documentation */ clocks 566 drivers/net/hamradio/dmascc.c priv->param.clocks = TCTRxCP | RCRTxCP; clocks 828 drivers/net/hamradio/dmascc.c write_scc(priv, R11, priv->param.clocks); clocks 829 drivers/net/hamradio/dmascc.c if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) { clocks 83 drivers/staging/board/armadillo800eva.c .clocks = lcdc0_clocks, clocks 177 drivers/staging/board/board.c board_staging_register_clock(&dev->clocks[i]); clocks 18 drivers/staging/board/board.h const struct board_staging_clk *clocks; clocks 195 drivers/staging/media/hantro/hantro.h struct clk_bulk_data *clocks; clocks 101 drivers/staging/media/hantro/hantro_drv.c clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); clocks 185 drivers/staging/media/hantro/hantro_drv.c ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks); clocks 755 drivers/staging/media/hantro/hantro_drv.c vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks, clocks 756 drivers/staging/media/hantro/hantro_drv.c sizeof(*vpu->clocks), GFP_KERNEL); clocks 757 drivers/staging/media/hantro/hantro_drv.c if (!vpu->clocks) clocks 761 drivers/staging/media/hantro/hantro_drv.c vpu->clocks[i].id = vpu->variant->clk_names[i]; clocks 763 drivers/staging/media/hantro/hantro_drv.c vpu->clocks); clocks 823 drivers/staging/media/hantro/hantro_drv.c ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); clocks 881 drivers/staging/media/hantro/hantro_drv.c clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); clocks 899 drivers/staging/media/hantro/hantro_drv.c clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); clocks 145 drivers/staging/media/hantro/rk3288_vpu_hw.c clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); clocks 131 drivers/staging/media/hantro/rk3399_vpu_hw.c clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); clocks 954 drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c component->clocks = rmsg->u.component_create_reply.clock_num; clocks 958 drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c component->inputs, component->outputs, component->clocks); clocks 1670 drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c for (idx = 0; idx < component->clocks; idx++) { clocks 89 drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h u32 clocks; /* Number of clock ports */ clocks 82 include/soc/tegra/bpmp.h struct tegra_bpmp_clk **clocks; clocks 54 include/trace/events/fsi_master_gpio.h TP_PROTO(const struct fsi_master_gpio *master, int clocks), clocks 55 include/trace/events/fsi_master_gpio.h TP_ARGS(master, clocks), clocks 58 include/trace/events/fsi_master_gpio.h __field(int, clocks) clocks 62 include/trace/events/fsi_master_gpio.h __entry->clocks = clocks; clocks 65 include/trace/events/fsi_master_gpio.h __entry->master_idx, __entry->clocks clocks 1441 scripts/dtc/checks.c WARNING_PROPERTY_PHANDLE_CELLS(clocks, "clocks", "#clock-cells"); clocks 127 sound/isa/cs423x/cs4236_lib.c static const struct snd_ratnum clocks[CLOCKS] = { clocks 140 sound/isa/cs423x/cs4236_lib.c .rats = clocks, clocks 276 sound/isa/es1688/es1688_lib.c static const struct snd_ratnum clocks[2] = { clocks 293 sound/isa/es1688/es1688_lib.c .rats = clocks, clocks 301 sound/isa/es1688/es1688_lib.c if (runtime->rate_num == clocks[0].num) clocks 1769 sound/pci/echoaudio/echoaudio.c int detected, clocks, bit, src; clocks 1780 sound/pci/echoaudio/echoaudio.c clocks = 0; clocks 1786 sound/pci/echoaudio/echoaudio.c clocks |= 1 << src; clocks 1789 sound/pci/echoaudio/echoaudio.c ucontrol->value.integer.value[5] = clocks; clocks 424 sound/pci/es1938.c static const struct snd_ratnum clocks[2] = { clocks 441 sound/pci/es1938.c .rats = clocks, clocks 451 sound/pci/es1938.c if (runtime->rate_num == clocks[0].num) clocks 676 sound/soc/codecs/tlv320aic32x4.c struct clk_bulk_data clocks[] = { clocks 684 sound/soc/codecs/tlv320aic32x4.c ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); clocks 730 sound/soc/codecs/tlv320aic32x4.c if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) clocks 733 sound/soc/codecs/tlv320aic32x4.c clk_set_rate(clocks[0].clk, clocks 736 sound/soc/codecs/tlv320aic32x4.c clk_set_rate(clocks[1].clk, clocks 739 sound/soc/codecs/tlv320aic32x4.c clk_set_rate(clocks[2].clk, clocks 744 sound/soc/codecs/tlv320aic32x4.c clk_set_rate(clocks[3].clk, clocks 747 sound/soc/codecs/tlv320aic32x4.c clk_set_rate(clocks[4].clk, clocks 752 sound/soc/codecs/tlv320aic32x4.c clk_set_rate(clocks[5].clk, clocks 827 sound/soc/codecs/tlv320aic32x4.c struct clk_bulk_data clocks[] = { clocks 833 sound/soc/codecs/tlv320aic32x4.c ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); clocks 839 sound/soc/codecs/tlv320aic32x4.c ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); clocks 852 sound/soc/codecs/tlv320aic32x4.c clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); clocks 941 sound/soc/codecs/tlv320aic32x4.c struct clk_bulk_data clocks[] = { clocks 948 sound/soc/codecs/tlv320aic32x4.c ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); clocks 963 sound/soc/codecs/tlv320aic32x4.c clk_set_parent(clocks[0].clk, clocks[1].clk); clocks 964 sound/soc/codecs/tlv320aic32x4.c clk_set_parent(clocks[2].clk, clocks[3].clk); clocks 38 sound/soc/hisilicon/hi6210-i2s.c int clocks; clocks 103 sound/soc/hisilicon/hi6210-i2s.c for (n = 0; n < i2s->clocks; n++) { clocks 176 sound/soc/hisilicon/hi6210-i2s.c for (n = 0; n < i2s->clocks; n++) clocks 575 sound/soc/hisilicon/hi6210-i2s.c i2s->clocks++; clocks 580 sound/soc/hisilicon/hi6210-i2s.c i2s->clocks++; clocks 150 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c struct clk *clocks[MT8173_CLK_NUM]; clocks 330 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M], clocks 332 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M], clocks 353 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], clocks 354 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c afe_priv->clocks[MT8173_CLK_I2S3_B]); clocks 367 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], clocks 368 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c afe_priv->clocks[MT8173_CLK_I2S3_B]); clocks 380 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], clocks 382 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c afe_priv->clocks[MT8173_CLK_I2S3_B], clocks 964 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); clocks 965 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); clocks 966 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); clocks 967 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]); clocks 968 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); clocks 969 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); clocks 970 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); clocks 980 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); clocks 984 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); clocks 988 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); clocks 992 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]); clocks 996 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]); clocks 999 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]); clocks 1002 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]); clocks 1021 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); clocks 1023 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); clocks 1025 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); clocks 1027 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); clocks 1029 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); clocks 1031 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); clocks 1041 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); clocks 1042 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c if (IS_ERR(afe_priv->clocks[i])) { clocks 1045 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c return PTR_ERR(afe_priv->clocks[i]); clocks 1048 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */ clocks 1049 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */