clock_state        62 drivers/gpu/drm/amd/display/dc/dm_services_types.h 	enum dm_pp_clocks_state clock_state;
clock_state        70 drivers/staging/media/soc_camera/soc_camera.c 		    !test_and_set_bit(0, &ssdd->clock_state))) {
clock_state       132 drivers/staging/media/soc_camera/soc_camera.c 	if (clk && (!ssdd->unbalanced_power || test_and_clear_bit(0, &ssdd->clock_state)))
clock_state        53 drivers/thermal/clock_cooling.c 	unsigned long clock_state;
clock_state       231 drivers/thermal/clock_cooling.c 	if (ccdev->clock_state == cooling_state)
clock_state       241 drivers/thermal/clock_cooling.c 	ccdev->clock_state = cooling_state;
clock_state       328 drivers/thermal/clock_cooling.c 	*state = ccdev->clock_state;
clock_state       414 drivers/thermal/clock_cooling.c 	ccdev->clock_state = 0;
clock_state       143 include/media/soc_camera.h 	unsigned long clock_state;
clock_state       203 include/media/soc_camera.h 	unsigned long clock_state;
clock_state      1213 include/soc/tegra/bpmp-abi.h 	uint32_t clock_state;
clock_state        50 sound/pci/echoaudio/darla20_dsp.c 	chip->clock_state = GD_CLOCK_UNDEF;
clock_state        90 sound/pci/echoaudio/darla20_dsp.c 	u8 clock_state, spdif_status;
clock_state        97 sound/pci/echoaudio/darla20_dsp.c 		clock_state = GD_CLOCK_44;
clock_state       101 sound/pci/echoaudio/darla20_dsp.c 		clock_state = GD_CLOCK_48;
clock_state       105 sound/pci/echoaudio/darla20_dsp.c 		clock_state = GD_CLOCK_NOCHANGE;
clock_state       110 sound/pci/echoaudio/darla20_dsp.c 	if (chip->clock_state == clock_state)
clock_state       111 sound/pci/echoaudio/darla20_dsp.c 		clock_state = GD_CLOCK_NOCHANGE;
clock_state       116 sound/pci/echoaudio/darla20_dsp.c 	chip->comm_page->gd_clock_state = clock_state;
clock_state       121 sound/pci/echoaudio/darla20_dsp.c 	if (clock_state != GD_CLOCK_NOCHANGE)
clock_state       122 sound/pci/echoaudio/darla20_dsp.c 		chip->clock_state = clock_state;
clock_state       372 sound/pci/echoaudio/echoaudio.h 	u8 clock_state;			/* Gina20, Darla20, Darla24 - only */
clock_state        54 sound/pci/echoaudio/gina20_dsp.c 	chip->clock_state = GD_CLOCK_UNDEF;
clock_state       106 sound/pci/echoaudio/gina20_dsp.c 	u8 clock_state, spdif_status;
clock_state       113 sound/pci/echoaudio/gina20_dsp.c 		clock_state = GD_CLOCK_44;
clock_state       117 sound/pci/echoaudio/gina20_dsp.c 		clock_state = GD_CLOCK_48;
clock_state       121 sound/pci/echoaudio/gina20_dsp.c 		clock_state = GD_CLOCK_NOCHANGE;
clock_state       126 sound/pci/echoaudio/gina20_dsp.c 	if (chip->clock_state == clock_state)
clock_state       127 sound/pci/echoaudio/gina20_dsp.c 		clock_state = GD_CLOCK_NOCHANGE;
clock_state       132 sound/pci/echoaudio/gina20_dsp.c 	chip->comm_page->gd_clock_state = clock_state;
clock_state       137 sound/pci/echoaudio/gina20_dsp.c 	if (clock_state != GD_CLOCK_NOCHANGE)
clock_state       138 sound/pci/echoaudio/gina20_dsp.c 		chip->clock_state = clock_state;
clock_state       155 sound/pci/echoaudio/gina20_dsp.c 		chip->clock_state = GD_CLOCK_UNDEF;
clock_state       165 sound/pci/echoaudio/gina20_dsp.c 		chip->clock_state = GD_CLOCK_SPDIFIN;