clock_cntl       1799 drivers/gpu/drm/amd/amdgpu/cik.c 	u32 clock_cntl, pc;
clock_cntl       1805 drivers/gpu/drm/amd/amdgpu/cik.c 	clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
clock_cntl       1807 drivers/gpu/drm/amd/amdgpu/cik.c 	if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
clock_cntl       1011 drivers/gpu/drm/amd/amdgpu/vi.c 	u32 clock_cntl, pc;
clock_cntl       1017 drivers/gpu/drm/amd/amdgpu/vi.c 	clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
clock_cntl       1019 drivers/gpu/drm/amd/amdgpu/vi.c 	if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
clock_cntl       3038 drivers/video/fbdev/aty/atyfb_base.c 		u8 clock_cntl;
clock_cntl       3057 drivers/video/fbdev/aty/atyfb_base.c 		clock_cntl = aty_ld_8(CLOCK_CNTL, par);
clock_cntl       3070 drivers/video/fbdev/aty/atyfb_base.c 		N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)];
clock_cntl       3075 drivers/video/fbdev/aty/atyfb_base.c 		P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) |
clock_cntl       3076 drivers/video/fbdev/aty/atyfb_base.c 		                     ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)];