clock_cfg         401 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			struct dc_clock_config *clock_cfg)
clock_cfg         405 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
clock_cfg         406 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
clock_cfg         407 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
clock_cfg         408 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
clock_cfg         411 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
clock_cfg         412 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
clock_cfg         413 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
clock_cfg         414 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
clock_cfg          51 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h 			struct dc_clock_config *clock_cfg);
clock_cfg        2533 drivers/gpu/drm/amd/display/dc/core/dc.c void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
clock_cfg        2536 drivers/gpu/drm/amd/display/dc/core/dc.c 		dc->hwss.get_clock(dc, clock_type, clock_cfg);
clock_cfg        1067 drivers/gpu/drm/amd/display/dc/dc.h void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
clock_cfg        3264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_clock_config clock_cfg = {0};
clock_cfg        3269 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 						context, clock_type, &clock_cfg);
clock_cfg        3274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (clk_khz > clock_cfg.max_clock_khz)
clock_cfg        3277 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (clk_khz < clock_cfg.min_clock_khz)
clock_cfg        3280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
clock_cfg        3300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			struct dc_clock_config *clock_cfg)
clock_cfg        3305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
clock_cfg         182 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 			struct dc_clock_config *clock_cfg);
clock_cfg         340 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 			struct dc_clock_config *clock_cfg);
clock_cfg         223 drivers/net/ethernet/cavium/common/cavium_ptp.c 	u64 clock_cfg;
clock_cfg         272 drivers/net/ethernet/cavium/common/cavium_ptp.c 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
clock_cfg         273 drivers/net/ethernet/cavium/common/cavium_ptp.c 	clock_cfg |= PTP_CLOCK_CFG_PTP_EN;
clock_cfg         274 drivers/net/ethernet/cavium/common/cavium_ptp.c 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
clock_cfg         289 drivers/net/ethernet/cavium/common/cavium_ptp.c 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
clock_cfg         290 drivers/net/ethernet/cavium/common/cavium_ptp.c 	clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
clock_cfg         291 drivers/net/ethernet/cavium/common/cavium_ptp.c 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
clock_cfg         311 drivers/net/ethernet/cavium/common/cavium_ptp.c 	u64 clock_cfg;
clock_cfg         318 drivers/net/ethernet/cavium/common/cavium_ptp.c 	clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
clock_cfg         319 drivers/net/ethernet/cavium/common/cavium_ptp.c 	clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
clock_cfg         320 drivers/net/ethernet/cavium/common/cavium_ptp.c 	writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);