clksrc_base        23 drivers/clocksource/timer-fsl-ftm.c 	void __iomem *clksrc_base;
clksrc_base       108 drivers/clocksource/timer-fsl-ftm.c 	return ftm_readl(priv->clksrc_base + FTM_CNT);
clksrc_base       217 drivers/clocksource/timer-fsl-ftm.c 	ftm_writel(0x00, priv->clksrc_base + FTM_CNTIN);
clksrc_base       218 drivers/clocksource/timer-fsl-ftm.c 	ftm_writel(~0u, priv->clksrc_base + FTM_MOD);
clksrc_base       220 drivers/clocksource/timer-fsl-ftm.c 	ftm_reset_counter(priv->clksrc_base);
clksrc_base       223 drivers/clocksource/timer-fsl-ftm.c 	err = clocksource_mmio_init(priv->clksrc_base + FTM_CNT, "fsl-ftm",
clksrc_base       231 drivers/clocksource/timer-fsl-ftm.c 	ftm_counter_enable(priv->clksrc_base);
clksrc_base       320 drivers/clocksource/timer-fsl-ftm.c 	priv->clksrc_base = of_iomap(np, 1);
clksrc_base       321 drivers/clocksource/timer-fsl-ftm.c 	if (!priv->clksrc_base) {
clksrc_base       354 drivers/clocksource/timer-fsl-ftm.c 	iounmap(priv->clksrc_base);
clksrc_base        52 drivers/clocksource/timer-oxnas-rps.c 	void __iomem *clksrc_base;
clksrc_base       191 drivers/clocksource/timer-oxnas-rps.c 	writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG);
clksrc_base       193 drivers/clocksource/timer-oxnas-rps.c 			rps->clksrc_base + TIMER_CTRL_REG);
clksrc_base       195 drivers/clocksource/timer-oxnas-rps.c 	timer_sched_base = rps->clksrc_base + TIMER_CURR_REG;
clksrc_base       245 drivers/clocksource/timer-oxnas-rps.c 	rps->clksrc_base = base + TIMER2_REG_OFFSET;
clksrc_base       249 drivers/clocksource/timer-oxnas-rps.c 	writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG);
clksrc_base       251 drivers/clocksource/timer-oxnas-rps.c 	writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG);
clksrc_base       253 drivers/clocksource/timer-oxnas-rps.c 	writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG);
clksrc_base        32 drivers/clocksource/timer-vf-pit.c static void __iomem *clksrc_base;
clksrc_base        53 drivers/clocksource/timer-vf-pit.c 	return ~__raw_readl(clksrc_base + PITCVAL);
clksrc_base        59 drivers/clocksource/timer-vf-pit.c 	__raw_writel(0, clksrc_base + PITTCTRL);
clksrc_base        60 drivers/clocksource/timer-vf-pit.c 	__raw_writel(~0UL, clksrc_base + PITLDVAL);
clksrc_base        61 drivers/clocksource/timer-vf-pit.c 	__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
clksrc_base        64 drivers/clocksource/timer-vf-pit.c 	return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
clksrc_base       173 drivers/clocksource/timer-vf-pit.c 	clksrc_base = timer_base + PITn_OFFSET(2);